[llvm] MIPSr6: Set FMAXNUM and FMINNUM as Legal (PR #139009)
YunQiang Su via llvm-commits
llvm-commits at lists.llvm.org
Wed May 7 22:07:14 PDT 2025
https://github.com/wzssyqa updated https://github.com/llvm/llvm-project/pull/139009
>From df4706902df5b7dcdf1e7ba5ed289b6b806419e9 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Thu, 8 May 2025 11:10:57 +0800
Subject: [PATCH 1/2] MIPSr6: Set FMAXNUM and FMINNUM as Legal
Now we define FMAXNUM and FMINNUM as IEEE754-2008 with +0.0>-0.0.
MIPSr6's fmax/fmin just follow this rules full.
FMAXNUM_IEEE and FMINNUM_IEEE will be removed in future once:
1. Fixes FMAXNUM/FMINNUM for all targets
2. The use of FMAXNUM_IEEE/FMINNUM_IEEE are not used by middle
end anymore.
---
llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 12 +++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 8 +-
llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll | 85 +++++++++-------------
3 files changed, 49 insertions(+), 56 deletions(-)
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 27b9ce60ba826..fead376b8c338 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -1122,15 +1122,27 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(fmaxnum_ieee f32:$lhs, f32:$rhs),
(MAX_S f32:$lhs, f32:$rhs)>,
ISA_MIPS32R6;
+ def : MipsPat<(fmaxnum f32:$lhs, f32:$rhs),
+ (MAX_S f32:$lhs, f32:$rhs)>,
+ ISA_MIPS32R6;
def : MipsPat<(fmaxnum_ieee f64:$lhs, f64:$rhs),
(MAX_D f64:$lhs, f64:$rhs)>,
ISA_MIPS32R6;
+ def : MipsPat<(fmaxnum f64:$lhs, f64:$rhs),
+ (MAX_D f64:$lhs, f64:$rhs)>,
+ ISA_MIPS32R6;
def : MipsPat<(fminnum_ieee f32:$lhs, f32:$rhs),
(MIN_S f32:$lhs, f32:$rhs)>,
ISA_MIPS32R6;
+ def : MipsPat<(fminnum f32:$lhs, f32:$rhs),
+ (MIN_S f32:$lhs, f32:$rhs)>,
+ ISA_MIPS32R6;
def : MipsPat<(fminnum_ieee f64:$lhs, f64:$rhs),
(MIN_D f64:$lhs, f64:$rhs)>,
ISA_MIPS32R6;
+ def : MipsPat<(fminnum f64:$lhs, f64:$rhs),
+ (MIN_D f64:$lhs, f64:$rhs)>,
+ ISA_MIPS32R6;
def : MipsPat<(f32 (fcanonicalize f32:$src)),
(MIN_S f32:$src, f32:$src)>,
ISA_MIPS32R6;
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 55fc636d3c781..4534f2a877030 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -365,12 +365,12 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
if (Subtarget.hasMips32r6()) {
setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
- setOperationAction(ISD::FMINNUM, MVT::f32, Expand);
- setOperationAction(ISD::FMAXNUM, MVT::f32, Expand);
+ setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
+ setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
- setOperationAction(ISD::FMINNUM, MVT::f64, Expand);
- setOperationAction(ISD::FMAXNUM, MVT::f64, Expand);
+ setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
+ setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
setOperationAction(ISD::IS_FPCLASS, MVT::f32, Legal);
setOperationAction(ISD::IS_FPCLASS, MVT::f64, Legal);
} else {
diff --git a/llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll b/llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll
index 2a0ad07474c09..4c337392a7a26 100644
--- a/llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll
+++ b/llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll
@@ -1,80 +1,61 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc %s -mtriple=mipsisa32r6el-linux-gnu -o - | \
; RUN: FileCheck %s --check-prefix=MIPS32R6EL
; RUN: llc %s -mtriple=mipsisa64r6el-linux-gnuabi64 -o - | \
; RUN: FileCheck %s --check-prefix=MIPS64R6EL
define float @mins(float %x, float %y) {
-; MIPS32R6EL-LABEL: mins
-; MIPS32R6EL: # %bb.0:
-; MIPS32R6EL-NEXT: min.s $f0, $f14, $f14
-; MIPS32R6EL-NEXT: min.s $f1, $f12, $f12
-; MIPS32R6EL-NEXT: jr $ra
-; MIPS32R6EL-NEXT: min.s $f0, $f1, $f0
+; MIPS32R6EL-LABEL: mins:
+; MIPS32R6EL: # %bb.0:
+; MIPS32R6EL-NEXT: jr $ra
+; MIPS32R6EL-NEXT: min.s $f0, $f12, $f14
;
-; MIPS64R6EL-LABEL: mins
-; MIPS64R6EL: # %bb.0:
-; MIPS64R6EL-NEXT: min.s $f0, $f13, $f13
-; MIPS64R6EL-NEXT: min.s $f1, $f12, $f12
-; MIPS64R6EL-NEXT: jr $ra
-; MIPS64R6EL-NEXT: min.s $f0, $f1, $f0
-
+; MIPS64R6EL-LABEL: mins:
+; MIPS64R6EL: # %bb.0:
+; MIPS64R6EL-NEXT: jr $ra
+; MIPS64R6EL-NEXT: min.s $f0, $f12, $f13
%r = tail call float @llvm.minnum.f32(float %x, float %y)
ret float %r
}
define float @maxs(float %x, float %y) {
-; MIPS32R6EL-LABEL: maxs
-; MIPS32R6EL: # %bb.0:
-; MIPS32R6EL-NEXT: min.s $f0, $f14, $f14
-; MIPS32R6EL-NEXT: min.s $f1, $f12, $f12
-; MIPS32R6EL-NEXT: jr $ra
-; MIPS32R6EL-NEXT: max.s $f0, $f1, $f0
+; MIPS32R6EL-LABEL: maxs:
+; MIPS32R6EL: # %bb.0:
+; MIPS32R6EL-NEXT: jr $ra
+; MIPS32R6EL-NEXT: max.s $f0, $f12, $f14
;
-; MIPS64R6EL-LABEL: maxs
-; MIPS64R6EL: # %bb.0:
-; MIPS64R6EL-NEXT: min.s $f0, $f13, $f13
-; MIPS64R6EL-NEXT: min.s $f1, $f12, $f12
-; MIPS64R6EL-NEXT: jr $ra
-; MIPS64R6EL-NEXT: max.s $f0, $f1, $f0
-
+; MIPS64R6EL-LABEL: maxs:
+; MIPS64R6EL: # %bb.0:
+; MIPS64R6EL-NEXT: jr $ra
+; MIPS64R6EL-NEXT: max.s $f0, $f12, $f13
%r = tail call float @llvm.maxnum.f32(float %x, float %y)
ret float %r
}
define double @mind(double %x, double %y) {
-; MIPS32R6EL-LABEL: mind
-; MIPS32R6EL: # %bb.0:
-; MIPS32R6EL-NEXT: min.d $f0, $f14, $f14
-; MIPS32R6EL-NEXT: min.d $f1, $f12, $f12
-; MIPS32R6EL-NEXT: jr $ra
-; MIPS32R6EL-NEXT: min.d $f0, $f1, $f0
+; MIPS32R6EL-LABEL: mind:
+; MIPS32R6EL: # %bb.0:
+; MIPS32R6EL-NEXT: jr $ra
+; MIPS32R6EL-NEXT: min.d $f0, $f12, $f14
;
-; MIPS64R6EL-LABEL: mind
-; MIPS64R6EL: # %bb.0:
-; MIPS64R6EL-NEXT: min.d $f0, $f13, $f13
-; MIPS64R6EL-NEXT: min.d $f1, $f12, $f12
-; MIPS64R6EL-NEXT: jr $ra
-; MIPS64R6EL-NEXT: min.d $f0, $f1, $f0
-
+; MIPS64R6EL-LABEL: mind:
+; MIPS64R6EL: # %bb.0:
+; MIPS64R6EL-NEXT: jr $ra
+; MIPS64R6EL-NEXT: min.d $f0, $f12, $f13
%r = tail call double @llvm.minnum.f64(double %x, double %y)
ret double %r
}
define double @maxd(double %x, double %y) {
-; MIPS32R6EL-LABEL: maxd
-; MIPS32R6EL: # %bb.0:
-; MIPS32R6EL-NEXT: min.d $f0, $f14, $f14
-; MIPS32R6EL-NEXT: min.d $f1, $f12, $f12
-; MIPS32R6EL-NEXT: jr $ra
-; MIPS32R6EL-NEXT: max.d $f0, $f1, $f0
+; MIPS32R6EL-LABEL: maxd:
+; MIPS32R6EL: # %bb.0:
+; MIPS32R6EL-NEXT: jr $ra
+; MIPS32R6EL-NEXT: max.d $f0, $f12, $f14
;
-; MIPS64R6EL-LABEL: maxd
-; MIPS64R6EL: # %bb.0:
-; MIPS64R6EL-NEXT: min.d $f0, $f13, $f13
-; MIPS64R6EL-NEXT: min.d $f1, $f12, $f12
-; MIPS64R6EL-NEXT: jr $ra
-; MIPS64R6EL-NEXT: max.d $f0, $f1, $f0
-
+; MIPS64R6EL-LABEL: maxd:
+; MIPS64R6EL: # %bb.0:
+; MIPS64R6EL-NEXT: jr $ra
+; MIPS64R6EL-NEXT: max.d $f0, $f12, $f13
%r = tail call double @llvm.maxnum.f64(double %x, double %y)
ret double %r
}
>From 49d911a9db57fc98de0dea296f9874320e177039 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Thu, 8 May 2025 13:07:00 +0800
Subject: [PATCH 2/2] Update testcase
---
llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 202 +++++++++++++---------
1 file changed, 121 insertions(+), 81 deletions(-)
diff --git a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
index 42b0f69181ab7..84d7c9688d239 100644
--- a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
+++ b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
@@ -396,57 +396,103 @@ define void @uitofp(i32 %a) {
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: addiu $sp, $sp, 8
;
-; MIPS64-N32-LABEL: uitofp:
-; MIPS64-N32: # %bb.0: # %entry
-; MIPS64-N32-NEXT: addiu $sp, $sp, -16
-; MIPS64-N32-NEXT: .cfi_def_cfa_offset 16
-; MIPS64-N32-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp)))
-; MIPS64-N32-NEXT: addu $1, $1, $25
-; MIPS64-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
-; MIPS64-N32-NEXT: lui $2, 17200
-; MIPS64-N32-NEXT: sw $2, 12($sp)
+; MIPS64R5-N32-LABEL: uitofp:
+; MIPS64R5-N32: # %bb.0: # %entry
+; MIPS64R5-N32-NEXT: addiu $sp, $sp, -16
+; MIPS64R5-N32-NEXT: .cfi_def_cfa_offset 16
+; MIPS64R5-N32-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp)))
+; MIPS64R5-N32-NEXT: addu $1, $1, $25
+; MIPS64R5-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
+; MIPS64R5-N32-NEXT: lui $2, 17200
+; MIPS64R5-N32-NEXT: sw $2, 12($sp)
; MIPS64R5-N32-NEXT: sll $2, $4, 0
; MIPS64R5-N32-NEXT: sw $2, 8($sp)
-; MIPSR6-N32-NEXT: sw $4, 8($sp)
-; MIPS64-N32-NEXT: lw $2, %got_page(.LCPI5_0)($1)
-; MIPS64-N32-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
-; MIPS64-N32-NEXT: ldc1 $f1, 8($sp)
-; MIPS64-N32-NEXT: sub.d $f0, $f1, $f0
-; MIPS64-N32-NEXT: dmfc1 $2, $f0
-; MIPS64-N32-NEXT: fill.d $w0, $2
-; MIPS64-N32-NEXT: fexdo.w $w0, $w0, $w0
-; MIPS64-N32-NEXT: fexdo.h $w0, $w0, $w0
-; MIPS64-N32-NEXT: lw $1, %got_disp(h)($1)
-; MIPS64-N32-NEXT: copy_u.h $2, $w0[0]
-; MIPS64-N32-NEXT: sh $2, 0($1)
-; MIPS64-N32-NEXT: jr $ra
-; MIPS64-N32-NEXT: addiu $sp, $sp, 16
+; MIPS64R5-N32-NEXT: lw $2, %got_page(.LCPI5_0)($1)
+; MIPS64R5-N32-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
+; MIPS64R5-N32-NEXT: ldc1 $f1, 8($sp)
+; MIPS64R5-N32-NEXT: sub.d $f0, $f1, $f0
+; MIPS64R5-N32-NEXT: dmfc1 $2, $f0
+; MIPS64R5-N32-NEXT: fill.d $w0, $2
+; MIPS64R5-N32-NEXT: fexdo.w $w0, $w0, $w0
+; MIPS64R5-N32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPS64R5-N32-NEXT: lw $1, %got_disp(h)($1)
+; MIPS64R5-N32-NEXT: copy_u.h $2, $w0[0]
+; MIPS64R5-N32-NEXT: sh $2, 0($1)
+; MIPS64R5-N32-NEXT: jr $ra
+; MIPS64R5-N32-NEXT: addiu $sp, $sp, 16
;
-; MIPS64-N64-LABEL: uitofp:
-; MIPS64-N64: # %bb.0: # %entry
-; MIPS64-N64-NEXT: daddiu $sp, $sp, -16
-; MIPS64-N64-NEXT: .cfi_def_cfa_offset 16
-; MIPS64-N64-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp)))
-; MIPS64-N64-NEXT: daddu $1, $1, $25
-; MIPS64-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
-; MIPS64-N64-NEXT: lui $2, 17200
-; MIPS64-N64-NEXT: sw $2, 12($sp)
+; MIPS64R5-N64-LABEL: uitofp:
+; MIPS64R5-N64: # %bb.0: # %entry
+; MIPS64R5-N64-NEXT: daddiu $sp, $sp, -16
+; MIPS64R5-N64-NEXT: .cfi_def_cfa_offset 16
+; MIPS64R5-N64-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp)))
+; MIPS64R5-N64-NEXT: daddu $1, $1, $25
+; MIPS64R5-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
+; MIPS64R5-N64-NEXT: lui $2, 17200
+; MIPS64R5-N64-NEXT: sw $2, 12($sp)
; MIPS64R5-N64-NEXT: sll $2, $4, 0
; MIPS64R5-N64-NEXT: sw $2, 8($sp)
+; MIPS64R5-N64-NEXT: ld $2, %got_page(.LCPI5_0)($1)
+; MIPS64R5-N64-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
+; MIPS64R5-N64-NEXT: ldc1 $f1, 8($sp)
+; MIPS64R5-N64-NEXT: sub.d $f0, $f1, $f0
+; MIPS64R5-N64-NEXT: dmfc1 $2, $f0
+; MIPS64R5-N64-NEXT: fill.d $w0, $2
+; MIPS64R5-N64-NEXT: fexdo.w $w0, $w0, $w0
+; MIPS64R5-N64-NEXT: fexdo.h $w0, $w0, $w0
+; MIPS64R5-N64-NEXT: ld $1, %got_disp(h)($1)
+; MIPS64R5-N64-NEXT: copy_u.h $2, $w0[0]
+; MIPS64R5-N64-NEXT: sh $2, 0($1)
+; MIPS64R5-N64-NEXT: jr $ra
+; MIPS64R5-N64-NEXT: daddiu $sp, $sp, 16
+;
+; MIPSR6-N32-LABEL: uitofp:
+; MIPSR6-N32: # %bb.0: # %entry
+; MIPSR6-N32-NEXT: addiu $sp, $sp, -16
+; MIPSR6-N32-NEXT: .cfi_def_cfa_offset 16
+; MIPSR6-N32-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp)))
+; MIPSR6-N32-NEXT: addu $1, $1, $25
+; MIPSR6-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
+; MIPSR6-N32-NEXT: lui $2, 17200
+; MIPSR6-N32-NEXT: sw $2, 12($sp)
+; MIPSR6-N32-NEXT: sw $4, 8($sp)
+; MIPSR6-N32-NEXT: lw $2, %got_page(.LCPI5_0)($1)
+; MIPSR6-N32-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
+; MIPSR6-N32-NEXT: ldc1 $f1, 8($sp)
+; MIPSR6-N32-NEXT: sub.d $f0, $f1, $f0
+; MIPSR6-N32-NEXT: dmfc1 $2, $f0
+; MIPSR6-N32-NEXT: fill.d $w0, $2
+; MIPSR6-N32-NEXT: fexdo.w $w0, $w0, $w0
+; MIPSR6-N32-NEXT: fexdo.h $w0, $w0, $w0
+; MIPSR6-N32-NEXT: lw $1, %got_disp(h)($1)
+; MIPSR6-N32-NEXT: copy_u.h $2, $w0[0]
+; MIPSR6-N32-NEXT: sh $2, 0($1)
+; MIPSR6-N32-NEXT: jr $ra
+; MIPSR6-N32-NEXT: addiu $sp, $sp, 16
+;
+; MIPSR6-N64-LABEL: uitofp:
+; MIPSR6-N64: # %bb.0: # %entry
+; MIPSR6-N64-NEXT: daddiu $sp, $sp, -16
+; MIPSR6-N64-NEXT: .cfi_def_cfa_offset 16
+; MIPSR6-N64-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp)))
+; MIPSR6-N64-NEXT: daddu $1, $1, $25
+; MIPSR6-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
+; MIPSR6-N64-NEXT: lui $2, 17200
+; MIPSR6-N64-NEXT: sw $2, 12($sp)
; MIPSR6-N64-NEXT: sw $4, 8($sp)
-; MIPS64-N64-NEXT: ld $2, %got_page(.LCPI5_0)($1)
-; MIPS64-N64-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
-; MIPS64-N64-NEXT: ldc1 $f1, 8($sp)
-; MIPS64-N64-NEXT: sub.d $f0, $f1, $f0
-; MIPS64-N64-NEXT: dmfc1 $2, $f0
-; MIPS64-N64-NEXT: fill.d $w0, $2
-; MIPS64-N64-NEXT: fexdo.w $w0, $w0, $w0
-; MIPS64-N64-NEXT: fexdo.h $w0, $w0, $w0
-; MIPS64-N64-NEXT: ld $1, %got_disp(h)($1)
-; MIPS64-N64-NEXT: copy_u.h $2, $w0[0]
-; MIPS64-N64-NEXT: sh $2, 0($1)
-; MIPS64-N64-NEXT: jr $ra
-; MIPS64-N64-NEXT: daddiu $sp, $sp, 16
+; MIPSR6-N64-NEXT: ld $2, %got_page(.LCPI5_0)($1)
+; MIPSR6-N64-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
+; MIPSR6-N64-NEXT: ldc1 $f1, 8($sp)
+; MIPSR6-N64-NEXT: sub.d $f0, $f1, $f0
+; MIPSR6-N64-NEXT: dmfc1 $2, $f0
+; MIPSR6-N64-NEXT: fill.d $w0, $2
+; MIPSR6-N64-NEXT: fexdo.w $w0, $w0, $w0
+; MIPSR6-N64-NEXT: fexdo.h $w0, $w0, $w0
+; MIPSR6-N64-NEXT: ld $1, %got_disp(h)($1)
+; MIPSR6-N64-NEXT: copy_u.h $2, $w0[0]
+; MIPSR6-N64-NEXT: sh $2, 0($1)
+; MIPSR6-N64-NEXT: jr $ra
+; MIPSR6-N64-NEXT: daddiu $sp, $sp, 16
entry:
@@ -2466,14 +2512,13 @@ define void @fminnum(float %b) {
; MIPSR6-O32-NEXT: lui $2, %hi(_gp_disp)
; MIPSR6-O32-NEXT: addiu $2, $2, %lo(_gp_disp)
; MIPSR6-O32-NEXT: addu $1, $2, $25
-; MIPSR6-O32-NEXT: min.s $f0, $f12, $f12
; MIPSR6-O32-NEXT: lw $1, %got(g)($1)
; MIPSR6-O32-NEXT: lh $2, 0($1)
-; MIPSR6-O32-NEXT: fill.h $w1, $2
-; MIPSR6-O32-NEXT: fexupr.w $w1, $w1
-; MIPSR6-O32-NEXT: copy_s.w $2, $w1[0]
-; MIPSR6-O32-NEXT: mtc1 $2, $f1
-; MIPSR6-O32-NEXT: min.s $f0, $f1, $f0
+; MIPSR6-O32-NEXT: fill.h $w0, $2
+; MIPSR6-O32-NEXT: fexupr.w $w0, $w0
+; MIPSR6-O32-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-O32-NEXT: mtc1 $2, $f0
+; MIPSR6-O32-NEXT: min.s $f0, $f0, $f12
; MIPSR6-O32-NEXT: mfc1 $2, $f0
; MIPSR6-O32-NEXT: fill.w $w0, $2
; MIPSR6-O32-NEXT: fexdo.h $w0, $w0, $w0
@@ -2486,14 +2531,13 @@ define void @fminnum(float %b) {
; MIPSR6-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum)))
; MIPSR6-N32-NEXT: addu $1, $1, $25
; MIPSR6-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(fminnum)))
-; MIPSR6-N32-NEXT: min.s $f0, $f12, $f12
; MIPSR6-N32-NEXT: lw $1, %got_disp(g)($1)
; MIPSR6-N32-NEXT: lh $2, 0($1)
-; MIPSR6-N32-NEXT: fill.h $w1, $2
-; MIPSR6-N32-NEXT: fexupr.w $w1, $w1
-; MIPSR6-N32-NEXT: copy_s.w $2, $w1[0]
-; MIPSR6-N32-NEXT: mtc1 $2, $f1
-; MIPSR6-N32-NEXT: min.s $f0, $f1, $f0
+; MIPSR6-N32-NEXT: fill.h $w0, $2
+; MIPSR6-N32-NEXT: fexupr.w $w0, $w0
+; MIPSR6-N32-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-N32-NEXT: mtc1 $2, $f0
+; MIPSR6-N32-NEXT: min.s $f0, $f0, $f12
; MIPSR6-N32-NEXT: mfc1 $2, $f0
; MIPSR6-N32-NEXT: fill.w $w0, $2
; MIPSR6-N32-NEXT: fexdo.h $w0, $w0, $w0
@@ -2506,14 +2550,13 @@ define void @fminnum(float %b) {
; MIPSR6-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum)))
; MIPSR6-N64-NEXT: daddu $1, $1, $25
; MIPSR6-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(fminnum)))
-; MIPSR6-N64-NEXT: min.s $f0, $f12, $f12
; MIPSR6-N64-NEXT: ld $1, %got_disp(g)($1)
; MIPSR6-N64-NEXT: lh $2, 0($1)
-; MIPSR6-N64-NEXT: fill.h $w1, $2
-; MIPSR6-N64-NEXT: fexupr.w $w1, $w1
-; MIPSR6-N64-NEXT: copy_s.w $2, $w1[0]
-; MIPSR6-N64-NEXT: mtc1 $2, $f1
-; MIPSR6-N64-NEXT: min.s $f0, $f1, $f0
+; MIPSR6-N64-NEXT: fill.h $w0, $2
+; MIPSR6-N64-NEXT: fexupr.w $w0, $w0
+; MIPSR6-N64-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-N64-NEXT: mtc1 $2, $f0
+; MIPSR6-N64-NEXT: min.s $f0, $f0, $f12
; MIPSR6-N64-NEXT: mfc1 $2, $f0
; MIPSR6-N64-NEXT: fill.w $w0, $2
; MIPSR6-N64-NEXT: fexdo.h $w0, $w0, $w0
@@ -2638,14 +2681,13 @@ define void @fmaxnum(float %b) {
; MIPSR6-O32-NEXT: lui $2, %hi(_gp_disp)
; MIPSR6-O32-NEXT: addiu $2, $2, %lo(_gp_disp)
; MIPSR6-O32-NEXT: addu $1, $2, $25
-; MIPSR6-O32-NEXT: min.s $f0, $f12, $f12
; MIPSR6-O32-NEXT: lw $1, %got(g)($1)
; MIPSR6-O32-NEXT: lh $2, 0($1)
-; MIPSR6-O32-NEXT: fill.h $w1, $2
-; MIPSR6-O32-NEXT: fexupr.w $w1, $w1
-; MIPSR6-O32-NEXT: copy_s.w $2, $w1[0]
-; MIPSR6-O32-NEXT: mtc1 $2, $f1
-; MIPSR6-O32-NEXT: max.s $f0, $f1, $f0
+; MIPSR6-O32-NEXT: fill.h $w0, $2
+; MIPSR6-O32-NEXT: fexupr.w $w0, $w0
+; MIPSR6-O32-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-O32-NEXT: mtc1 $2, $f0
+; MIPSR6-O32-NEXT: max.s $f0, $f0, $f12
; MIPSR6-O32-NEXT: mfc1 $2, $f0
; MIPSR6-O32-NEXT: fill.w $w0, $2
; MIPSR6-O32-NEXT: fexdo.h $w0, $w0, $w0
@@ -2658,14 +2700,13 @@ define void @fmaxnum(float %b) {
; MIPSR6-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum)))
; MIPSR6-N32-NEXT: addu $1, $1, $25
; MIPSR6-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(fmaxnum)))
-; MIPSR6-N32-NEXT: min.s $f0, $f12, $f12
; MIPSR6-N32-NEXT: lw $1, %got_disp(g)($1)
; MIPSR6-N32-NEXT: lh $2, 0($1)
-; MIPSR6-N32-NEXT: fill.h $w1, $2
-; MIPSR6-N32-NEXT: fexupr.w $w1, $w1
-; MIPSR6-N32-NEXT: copy_s.w $2, $w1[0]
-; MIPSR6-N32-NEXT: mtc1 $2, $f1
-; MIPSR6-N32-NEXT: max.s $f0, $f1, $f0
+; MIPSR6-N32-NEXT: fill.h $w0, $2
+; MIPSR6-N32-NEXT: fexupr.w $w0, $w0
+; MIPSR6-N32-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-N32-NEXT: mtc1 $2, $f0
+; MIPSR6-N32-NEXT: max.s $f0, $f0, $f12
; MIPSR6-N32-NEXT: mfc1 $2, $f0
; MIPSR6-N32-NEXT: fill.w $w0, $2
; MIPSR6-N32-NEXT: fexdo.h $w0, $w0, $w0
@@ -2678,14 +2719,13 @@ define void @fmaxnum(float %b) {
; MIPSR6-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum)))
; MIPSR6-N64-NEXT: daddu $1, $1, $25
; MIPSR6-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(fmaxnum)))
-; MIPSR6-N64-NEXT: min.s $f0, $f12, $f12
; MIPSR6-N64-NEXT: ld $1, %got_disp(g)($1)
; MIPSR6-N64-NEXT: lh $2, 0($1)
-; MIPSR6-N64-NEXT: fill.h $w1, $2
-; MIPSR6-N64-NEXT: fexupr.w $w1, $w1
-; MIPSR6-N64-NEXT: copy_s.w $2, $w1[0]
-; MIPSR6-N64-NEXT: mtc1 $2, $f1
-; MIPSR6-N64-NEXT: max.s $f0, $f1, $f0
+; MIPSR6-N64-NEXT: fill.h $w0, $2
+; MIPSR6-N64-NEXT: fexupr.w $w0, $w0
+; MIPSR6-N64-NEXT: copy_s.w $2, $w0[0]
+; MIPSR6-N64-NEXT: mtc1 $2, $f0
+; MIPSR6-N64-NEXT: max.s $f0, $f0, $f12
; MIPSR6-N64-NEXT: mfc1 $2, $f0
; MIPSR6-N64-NEXT: fill.w $w0, $2
; MIPSR6-N64-NEXT: fexdo.h $w0, $w0, $w0
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