[llvm] [RISCV][Peephole] Checking regclass compatibility in VMV (PR #138844)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed May 7 05:33:36 PDT 2025
================
@@ -0,0 +1,145 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
+# RUN: -verify-machineinstrs | FileCheck %s
+
+--- |
+ source_filename = "reduced.ll"
+ target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+ target triple = "riscv64-unknown-linux-gnu"
+
+ define i32 @main() #0 {
+ entry:
+ %0 = tail call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer, i64 0)
+ %1 = tail call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> %0, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i1> zeroinitializer, i64 0, i64 0)
+ %2 = tail call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x i32> %1, <vscale x 1 x i32> zeroinitializer, <vscale x 1 x i1> zeroinitializer, i64 0, i64 0)
+ %3 = tail call target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) zeroinitializer, <vscale x 1 x i64> %2, i32 0)
+ call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %3, ptr null, i64 0, i64 6)
+ ret i32 0
+ }
+
+ declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, i64) #1
+
+ declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
+
+ declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i64, i64 immarg) #1
+
+ declare target("riscv.vector.tuple", <vscale x 8 x i8>, 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), <vscale x 1 x i64>, i32 immarg) #2
+
+ declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr captures(none), i64, i64 immarg) #3
+
+ attributes #0 = { "target-features"="+v" }
+ attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) "target-features"="+v" }
+ attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-features"="+v" }
+ attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) "target-features"="+v" }
+
+...
+---
+name: main
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+noPhis: false
+isSSA: true
+noVRegs: false
+hasFakeUses: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+ - { id: 0, class: vr, preferred-register: '', flags: [ ] }
+ - { id: 1, class: vrnov0, preferred-register: '', flags: [ ] }
+ - { id: 2, class: vr, preferred-register: '', flags: [ ] }
+ - { id: 3, class: vrnov0, preferred-register: '', flags: [ ] }
+ - { id: 4, class: vmv0, preferred-register: '', flags: [ ] }
+ - { id: 5, class: vrnov0, preferred-register: '', flags: [ ] }
+ - { id: 6, class: vrnov0, preferred-register: '', flags: [ ] }
+ - { id: 7, class: vmv0, preferred-register: '', flags: [ ] }
+ - { id: 8, class: vr, preferred-register: '', flags: [ ] }
+ - { id: 9, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 10, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 11, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 12, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 13, class: vrn3m1, preferred-register: '', flags: [ ] }
+ - { id: 14, class: gpr, preferred-register: '', flags: [ ] }
+liveins: []
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ functionContext: ''
+ maxCallFrameSize: 4294967295
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: false
+ isCalleeSavedInfoValid: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack: []
+entry_values: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo:
+ varArgsFrameIndex: 0
+ varArgsSaveSize: 0
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: main
+ ; CHECK: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 $noreg, [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vmv0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: early-clobber %6:vrnov0 = PseudoVWMACC_VV_MF2_MASK [[PseudoVMV_V_I_M1_]], killed [[PseudoVXOR_VV_MF2_MASK]], [[PseudoVMV_V_I_MF2_]], [[COPY1]], 0, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[PseudoVMV_V_I_M1_1:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_0
+ ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_1
+ ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVMV_V_I_M1_1]], %subreg.sub_vrm1_2
+ ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG2]], killed %6, %subreg.sub_vrm1_0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: PseudoVSSEG3E64_V_M1 killed [[INSERT_SUBREG3]], [[COPY2]], 0, 6 /* e64 */ :: (store unknown-size into `ptr null`, align 8)
+ ; CHECK-NEXT: $x10 = COPY [[COPY2]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
+ %1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
+ %2:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ %4:vmv0 = COPY %2
+ %3:vrnov0 = PseudoVXOR_VV_MF2_MASK %1, %0, %0, %4, 0, 5 /* e32 */, 0 /* tu, mu */
----------------
lukel97 wrote:
Do we need the entire function or is %1 and %3 enough on its own to trigger the crash?
https://github.com/llvm/llvm-project/pull/138844
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