[llvm] [llvm] Ensure that soft float targets don't use float/vector code for memops. (PR #107022)

[Ulrich Weigand via llvm-commits]

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@@ -2023,6 +2023,11 @@ class TargetLoweringBase {
     return LLT();
   }
 
+  bool useIntScalarMemOps(const AttributeList &FuncAttributes) const {
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uweigand wrote:

As I see it, the term "soft float" has traditionally been used for one of two distinct concepts:
1) Hardware features associated with floating-point (and/or vector) are not available.  This includes instructions, but more importantly also *registers*.   These may not be available because the HW doesn't actually have them, or because they must not be used in the given context (e.g. Linux kernel code).
2) The ABI for passing floating-point (and/or vector) types does not use any floating-point (vector) HW features (specifically, registers).

Now clearly if we have no float/vector registers, we cannot use an ABI that requires them.   The inverse is not necessarily true - you could implement an ABI that does not use float registers, but the generated code is still allowed to use float registers within a function.  That's the case that I think sometimes causes confusion.

At least on SystemZ, the intent of the `-msoft-float` flag in all its permutations has always been both 1) and 2) - i.e. it implements a non-standard ABI, and also prohibits any use of floating-point or vector registers.


https://github.com/llvm/llvm-project/pull/107022