[llvm] [AMDGPU] Handle MachineOperandType global address in SIFoldOperands. (PR #135424)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri May 2 11:55:34 PDT 2025
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/135424
>From ea3c20aa84e4b74e0bc497c2a0e9b81aa3907f54 Mon Sep 17 00:00:00 2001
From: Akhilesh Moorthy <akhilesh.moorthy at amd.com>
Date: Wed, 23 Apr 2025 17:52:03 -0500
Subject: [PATCH 1/4] [AMDGPU] Handle MachineOperandType global address in
SIFoldOperands.
Fixes SWDEV-504645.
This patch handles the global operand type properly fixing the
bug : Assertion `(isFI() || isCPI() || isTargetIndex() ||
isJTI()) && "Wrong MachineOperand accessor"' failed.
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 4 ++
llvm/test/CodeGen/AMDGPU/swdev-504645.ll | 47 +++++++++++++++++++++++
2 files changed, 51 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/swdev-504645.ll
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 1547142a8d5c6..3cfbe14d4e7d2 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1161,6 +1161,10 @@ void SIFoldOperandsImpl::foldOperand(
if (OpToFold.isImm())
UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
+ else if (OpToFold.isGlobal())
+ UseMI->getOperand(1).ChangeToGA(OpToFold.getGlobal(),
+ OpToFold.getOffset(),
+ OpToFold.getTargetFlags());
else
UseMI->getOperand(1).ChangeToFrameIndex(OpToFold.getIndex());
UseMI->removeOperand(2); // Remove exec read (or src1 for readlane)
diff --git a/llvm/test/CodeGen/AMDGPU/swdev-504645.ll b/llvm/test/CodeGen/AMDGPU/swdev-504645.ll
new file mode 100644
index 0000000000000..3467a51cbc9b5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/swdev-504645.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs < %s | FileCheck %s
+
+define void @test_load_zext() {
+; CHECK-LABEL: test_load_zext:
+; CHECK: ; %bb.0: ; %.entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_mov_b32 s0, s33
+; CHECK-NEXT: s_mov_b32 s33, s32
+; CHECK-NEXT: s_or_saveexec_b64 s[2:3], -1
+; CHECK-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill
+; CHECK-NEXT: s_mov_b64 exec, s[2:3]
+; CHECK-NEXT: s_add_i32 s32, s32, 16
+; CHECK-NEXT: v_writelane_b32 v40, s0, 2
+; CHECK-NEXT: s_getpc_b64 s[0:1]
+; CHECK-NEXT: s_add_u32 s0, s0, test_buffer_load_sgpr_plus_imm_offset_noflags at gotpcrel32@lo+4
+; CHECK-NEXT: s_addc_u32 s1, s1, test_buffer_load_sgpr_plus_imm_offset_noflags at gotpcrel32@hi+12
+; CHECK-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
+; CHECK-NEXT: v_writelane_b32 v40, s30, 0
+; CHECK-NEXT: s_mov_b32 s0, DescriptorBuffer at abs32@lo
+; CHECK-NEXT: v_writelane_b32 v40, s31, 1
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_swappc_b64 s[30:31], s[2:3]
+; CHECK-NEXT: v_readlane_b32 s31, v40, 1
+; CHECK-NEXT: v_readlane_b32 s30, v40, 0
+; CHECK-NEXT: s_mov_b32 s32, s33
+; CHECK-NEXT: v_readlane_b32 s0, v40, 2
+; CHECK-NEXT: s_or_saveexec_b64 s[2:3], -1
+; CHECK-NEXT: scratch_load_dword v40, off, s33 ; 4-byte Folded Reload
+; CHECK-NEXT: s_mov_b64 exec, s[2:3]
+; CHECK-NEXT: s_mov_b32 s33, s0
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+.entry:
+ %0 = call i32 @llvm.amdgcn.reloc.constant(metadata !0)
+ call void @test_buffer_load_sgpr_plus_imm_offset_noflags(i32 %0)
+ ret void
+}
+
+declare void @test_buffer_load_sgpr_plus_imm_offset_noflags(i32 inreg)
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare i32 @llvm.amdgcn.reloc.constant(metadata) #0
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+
+!0 = !{!"DescriptorBuffer", i32 4, i32 8, i32 0, i32 0}
>From d259fb19d7d9b9d796af0b6775f036b471b610dc Mon Sep 17 00:00:00 2001
From: Akhilesh Moorthy <akhilesh.moorthy at amd.com>
Date: Thu, 24 Apr 2025 22:54:08 -0500
Subject: [PATCH 2/4] Patch with updated test case, based on feedback.
---
.../{swdev-504645.ll => swdev504645-global-fold.ll} | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
rename llvm/test/CodeGen/AMDGPU/{swdev-504645.ll => swdev504645-global-fold.ll} (73%)
diff --git a/llvm/test/CodeGen/AMDGPU/swdev-504645.ll b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
similarity index 73%
rename from llvm/test/CodeGen/AMDGPU/swdev-504645.ll
rename to llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
index 3467a51cbc9b5..1c8ef2adc6437 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev-504645.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s
define void @test_load_zext() {
; CHECK-LABEL: test_load_zext:
@@ -13,8 +13,8 @@ define void @test_load_zext() {
; CHECK-NEXT: s_add_i32 s32, s32, 16
; CHECK-NEXT: v_writelane_b32 v40, s0, 2
; CHECK-NEXT: s_getpc_b64 s[0:1]
-; CHECK-NEXT: s_add_u32 s0, s0, test_buffer_load_sgpr_plus_imm_offset_noflags at gotpcrel32@lo+4
-; CHECK-NEXT: s_addc_u32 s1, s1, test_buffer_load_sgpr_plus_imm_offset_noflags at gotpcrel32@hi+12
+; CHECK-NEXT: s_add_u32 s0, s0, has_spgr_args at gotpcrel32@lo+4
+; CHECK-NEXT: s_addc_u32 s1, s1, has_spgr_args at gotpcrel32@hi+12
; CHECK-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; CHECK-NEXT: v_writelane_b32 v40, s30, 0
; CHECK-NEXT: s_mov_b32 s0, DescriptorBuffer at abs32@lo
@@ -32,14 +32,13 @@ define void @test_load_zext() {
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
.entry:
- %0 = call i32 @llvm.amdgcn.reloc.constant(metadata !0)
- call void @test_buffer_load_sgpr_plus_imm_offset_noflags(i32 %0)
+ %reloc = call i32 @llvm.amdgcn.reloc.constant(metadata !0)
+ call void @has_spgr_args(i32 %reloc)
ret void
}
-declare void @test_buffer_load_sgpr_plus_imm_offset_noflags(i32 inreg)
+declare void @has_spgr_args(i32 inreg)
-; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i32 @llvm.amdgcn.reloc.constant(metadata) #0
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
>From 4f5dcb4a203ee3470a8868e4df7be4b6035ce5c2 Mon Sep 17 00:00:00 2001
From: Akhilesh Moorthy <akhilesh.moorthy at amd.com>
Date: Mon, 28 Apr 2025 00:10:35 -0500
Subject: [PATCH 3/4] Updated Patch, based on feedback.
---
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 8 +++++---
llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll | 6 ++----
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 3cfbe14d4e7d2..ff4ccca079100 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1161,12 +1161,14 @@ void SIFoldOperandsImpl::foldOperand(
if (OpToFold.isImm())
UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
- else if (OpToFold.isGlobal())
+ else if (OpToFold.isFI())
+ UseMI->getOperand(1).ChangeToFrameIndex(OpToFold.getIndex());
+ else {
+ assert(OpToFold.isGlobal());
UseMI->getOperand(1).ChangeToGA(OpToFold.getGlobal(),
OpToFold.getOffset(),
OpToFold.getTargetFlags());
- else
- UseMI->getOperand(1).ChangeToFrameIndex(OpToFold.getIndex());
+ }
UseMI->removeOperand(2); // Remove exec read (or src1 for readlane)
return;
}
diff --git a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
index 1c8ef2adc6437..db3f38576e78a 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s
define void @test_load_zext() {
; CHECK-LABEL: test_load_zext:
@@ -41,6 +41,4 @@ declare void @has_spgr_args(i32 inreg)
declare i32 @llvm.amdgcn.reloc.constant(metadata) #0
-attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
-
-!0 = !{!"DescriptorBuffer", i32 4, i32 8, i32 0, i32 0}
+!0 = !{!"DescriptorBuffer", i32 4, i32 8, i32 0, i32 0}
\ No newline at end of file
>From 89c7ff9e6d3c6232e635adf6e54d2dd196ec475d Mon Sep 17 00:00:00 2001
From: Matt Arsenault <arsenm2 at gmail.com>
Date: Fri, 2 May 2025 20:55:25 +0200
Subject: [PATCH 4/4] fix whitespace error
---
llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
index db3f38576e78a..c4af66e922e8d 100644
--- a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
+++ b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll
@@ -41,4 +41,4 @@ declare void @has_spgr_args(i32 inreg)
declare i32 @llvm.amdgcn.reloc.constant(metadata) #0
-!0 = !{!"DescriptorBuffer", i32 4, i32 8, i32 0, i32 0}
\ No newline at end of file
+!0 = !{!"DescriptorBuffer", i32 4, i32 8, i32 0, i32 0}
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