[llvm] [X86][BreakFalseDeps] Using reverse order for undef register selection (PR #137569)

[Simon Pilgrim via llvm-commits]

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@@ -1,4 +1,5 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Markup has been autogenerated by intel_update_markup.py ; INTEL
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RKSimon wrote:

huh?

https://github.com/llvm/llvm-project/pull/137569