[llvm] [WIP][AMDGPU][MC] Allow 128-bit rsrc register in MIMG instructions (PR #132264)

[Jun Wang via llvm-commits]

jwanggit86 wrote:

One concern here is that, because each MIMG instruction (except for gfx9) would have a new variant for 128-b rsrc reg, some TableGen generated tables would have a lot more entries, which is not desirable. To make things worse, while coding for gfx10 after pre-gfx9 was done, I ran into the following build error:
```
AMDGPUGenInstrInfo.inc:103942: error: narrowing conversion of '65742' from 'unsigned int' to 'short unsigned int' [-Wnarrowing]
```
After some investigation, I believe this is caused by the following in `AMDGPUGenInstrInfo.inc`
```
struct AMDGPUInstrTable {
  MCInstrDesc Insts[50704];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[21914];
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
  MCPhysReg ImplicitOps[83];
};

static constexpr unsigned AMDGPUImpOpBase = sizeof AMDGPUInstrTable::OperandInfo / (sizeof(MCPhysReg));

extern const AMDGPUInstrTable AMDGPUDescs = {
  {
    { 50703,    10,     1,      8,      2,      1,      0,      AMDGPUImpOpBase + 1,    2366,   0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000004002ULL },  // Inst #50703 = V_XOR_B32_sdwa_vi
```
Here, `AMDGPUImpOpBase` equals `21914 * 6/2 = 65742` which is out of the range of a short int. So, if I continue with the approach I'd have to modify the class `MCInstrDesc`. Another option is to look for a new approach. Pls let me know your thoughts. @arsenm @mbrkusanin @jayfoad @Sisyph 

https://github.com/llvm/llvm-project/pull/132264