[llvm] [LLVM][CodeGen][AArch64] Don't scalarise v8{f16,bf16} vsetcc operations. (PR #135398)

[Paul Walker via llvm-commits]

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@@ -841,18 +841,21 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     setOperationPromotedToType(ISD::FRINT,      V4Narrow, MVT::v4f32);
     setOperationPromotedToType(ISD::FNEARBYINT, V4Narrow, MVT::v4f32);
     setOperationPromotedToType(ISD::FCANONICALIZE, V4Narrow, MVT::v4f32);
+    setOperationPromotedToType(ISD::SETCC,         V4Narrow, MVT::v4f32);
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paulwalker-arm wrote:

Thanks, I'll add it to my TODO list to revisit. I have investigating this in the past and found uses that relied on the current behaviour. I recall things like using promotion to canonicalise all vector loads to integer vector loads.  Perhaps I misunderstood the code back then or the compiler has simply moved on. Hopefully the latter because like you say the current default doesn't feel much like promotion.

https://github.com/llvm/llvm-project/pull/135398