[llvm] [AArch64][SVE] Combine UXT[BHW] intrinsics to AND. (PR #137956)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

> Correct. This is one of the rare cases where we have to ignore the formatter errors.

That makes sense, thanks! :)

> This could be unfounded paranoia on my side but I've generally tried to avoid loosing information about which lanes are active because I figure it may be useful later on. This prompts two thoughts, one easy the other more involved:
> 
> 1. What about emitting an `sve.and_u` intrinsic so we maintain the predicate knowledge.  When this gets to ISel it'll still emit the desired AND immediate instruction.
> 
> 2. Should we canonicalise all `sve.uxt` intrinsics to `sve.and`? You'll still get the output you want but we will need ISEL patterns to emit UXT[B,H,S,B] when desirable (i.e. for sve.and(non-undef, no-all-active-predicate, mask).

I see what you mean, and I'm okay with either option. Do you have a preference?

I guess option (2) sounds more scalable and gives us a chance to improve the lowering for `svand_m` with all-ones 8/16/32-bit masks ([link](https://godbolt.org/z/P3nxMa5oE)), but we could equally address it separately.

https://github.com/llvm/llvm-project/pull/137956