[llvm] [AArch64][SVE] Combine UXT[BHW] intrinsics to AND. (PR #137956)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

This could be unfounded paranoia on my side but I've generally tried to avoid loosing information about which lanes are active because I figure it may be useful later on.  This prompts two thoughts, one easy the other more involved:
1. What about emitting an `sve.and_u` intrinsic so we maintain the predicate knowledge.  When this gets to ISel it'll still emit the desired AND immediate instruction.
2. Should we canonicalise all `sve.uxt` intrinsics to `sve.and`? You'll still get the output you want but we will need ISEL patterns to emit UXT[B,H,S,B] when desirable (i.e. for sve.and(non-undef, no-all-active-predicate, mask). 

https://github.com/llvm/llvm-project/pull/137956