[llvm] MachineScheduler: Improve instruction clustering (PR #137784)

[Jay Foad via llvm-commits]

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@@ -14204,23 +14204,23 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
 ; RV64ZVE32F-NEXT:    slli t2, t2, 8
 ; RV64ZVE32F-NEXT:    or a6, t0, a7
 ; RV64ZVE32F-NEXT:    or a2, a4, a2
-; RV64ZVE32F-NEXT:    lbu a4, 24(a0)
+; RV64ZVE32F-NEXT:    or a4, t2, t1
 ; RV64ZVE32F-NEXT:    lbu a7, 25(a0)
-; RV64ZVE32F-NEXT:    or t0, t2, t1
+; RV64ZVE32F-NEXT:    lbu t0, 24(a0)
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jayfoad wrote:

> Is the order important for RISCV?

See https://github.com/llvm/llvm-project/pull/75338#issuecomment-1874045768

According to @asb's explanation in the patch that introduced `ReorderWhileClustering`, the order is not too important. The rationale was more to do with not making arbitrary reorderings that could confuse someone trying to understand what the compiler was doing.

https://github.com/llvm/llvm-project/pull/137784