[llvm] MachineScheduler: Improve instruction clustering (PR #137784)

[via llvm-commits]

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@@ -14204,23 +14204,23 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
 ; RV64ZVE32F-NEXT:    slli t2, t2, 8
 ; RV64ZVE32F-NEXT:    or a6, t0, a7
 ; RV64ZVE32F-NEXT:    or a2, a4, a2
-; RV64ZVE32F-NEXT:    lbu a4, 24(a0)
+; RV64ZVE32F-NEXT:    or a4, t2, t1
 ; RV64ZVE32F-NEXT:    lbu a7, 25(a0)
-; RV64ZVE32F-NEXT:    or t0, t2, t1
+; RV64ZVE32F-NEXT:    lbu t0, 24(a0)
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ruiling wrote:

Is the order important for RISCV? Based on my understanding, memory op clustering did add a weak edge between the cluster candidates, but it is very fragile to be used to achieve certain instruction order. If you look at the scmp.ll test, the order of the memory instructions before the change is:
```
; RV32I-NEXT:    lw a6, 12(a0)
; RV32I-NEXT:    lw a3, 4(a0)
; RV32I-NEXT:    lw a7, 8(a0)
```
I hope the order of instructions be determined by tryCandidate(). For example, to order the memory instructions based on the immediate offset, maybe we can do like AArch64 (https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp#L77)?

https://github.com/llvm/llvm-project/pull/137784