[llvm] [X86][BreakFalseDeps] Using reverse order for undef register selection (PR #137569)

[Phoebe Wang via llvm-commits]

================
@@ -142,7 +144,12 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
 
   // FIXME: Once targets reserve registers instead of removing them from the
   // allocation order, we can simply use begin/end here.
-  ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
+  ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF, Reverse);
+  std::vector<MCPhysReg> ReverseOrder;
+  if (Reverse) {
+    llvm::append_range(ReverseOrder, reverse(RawOrder));
+    RawOrder = ArrayRef<MCPhysReg>(ReverseOrder);
+  }
----------------
phoebewang wrote:

The problem is not some registers are fast. They are all the same.

The intention here is to alter the order for the a specific pass. It doesn't solve the problem here if we just reverse register oder for all passes.

https://github.com/llvm/llvm-project/pull/137569