[llvm] [AMDGPU] Fix register class constraints for si-fold-operands pass when folding immediate into copies (PR #131387)

[via llvm-commits]

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@@ -1047,6 +1047,16 @@ void SIFoldOperandsImpl::foldOperand(
     if (MovOp == AMDGPU::COPY)
       return;
 
+    // Fold if the destination register class of the MOV instruction (ResRC)
+    // is a superclass of (or equal to) the destination register class of the COPY (DestRC).
+    // If this condition fails, folding would be illegal.
+    const MCInstrDesc &MovDesc = TII->get(MovOp);
+    if (MovDesc.getNumDefs() > 0 && MovDesc.operands()[0].RegClass != -1) {
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mssefat wrote:

Done, can you please review?

https://github.com/llvm/llvm-project/pull/131387