[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

[Pengcheng Wang via llvm-commits]

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@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                              NoSchedModel,
+                                              !listconcat(RVA23S64Features,
+                                              [FeatureStdExtZicsr,
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wangpc-pp wrote:

Zicsr is in `RVA23S64Features` already.

https://github.com/llvm/llvm-project/pull/123193