[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

[Tang Haojin via llvm-commits]

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@@ -553,6 +553,37 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                          NoSchedModel,
+                                          !listconcat(!listremove(RVA23S64Features,
+                                                      [FeatureStdExtZiccamoa,
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Tang-Haojin wrote:

> Then I think we should wait for the freeze of features. I don't think we will accept an intermediate version.

Hi @wangpc-pp, the KunMingHu-V2R2 version of the ISA strings has been frozen, and support for the "ziccamoa", "zihintntl", and "zawrs" extensions has also been updated. Please check https://github.com/OpenXiangShan/XiangShan/pull/4219 (This PR has only updated the isa string, and the support of these three extensions had been done before this PR).

https://github.com/llvm/llvm-project/pull/123193