[llvm] [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (PR #135882)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-rel-x86-64` running on `ml-opt-rel-x86-64-b1` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/16803

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
13.496 [2576/64/1221] Building AArch64GenPostLegalizeGILowering.inc...
13.602 [2575/64/1222] Building AArch64GenSystemOperands.inc...
13.624 [2574/64/1223] Building AVRGenAsmMatcher.inc...
13.643 [2573/64/1224] Building AVRGenAsmWriter.inc...
13.727 [2572/64/1225] Building ARMGenMCPseudoLowering.inc...
13.812 [2571/64/1226] Building ARMGenCallingConv.inc...
13.916 [2570/64/1227] Building AVRGenCallingConv.inc...
14.021 [2569/64/1228] Building AArch64GenMCCodeEmitter.inc...
14.206 [2568/64/1229] Building ARMGenAsmWriter.inc...
14.376 [2567/64/1230] Building AArch64GenDisassemblerTables.inc...
FAILED: lib/Target/AArch64/AArch64GenDisassemblerTables.inc /b/ml-opt-rel-x86-64-b1/build/lib/Target/AArch64/AArch64GenDisassemblerTables.inc 
cd /b/ml-opt-rel-x86-64-b1/build && /b/ml-opt-rel-x86-64-b1/build/bin/llvm-tblgen -gen-disassembler --num-to-skip-size=3 -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/AArch64 -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-rel-x86-64-b1/build/include -I/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/AArch64/AArch64.td --write-if-changed -o lib/Target/AArch64/AArch64GenDisassemblerTables.inc -d lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d
llvm-tblgen: /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/utils/TableGen/DecoderEmitter.cpp:150: void {anonymous}::DecoderTable::patchNumToSkip(size_t, uint32_t): Assertion `DestIdx > FixupIdx + NumToSkipSizeInBytes && "Expecting a forward jump in the decoding table"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /b/ml-opt-rel-x86-64-b1/build/bin/llvm-tblgen -gen-disassembler --num-to-skip-size=3 -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/AArch64 -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-rel-x86-64-b1/build/include -I/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/AArch64/AArch64.td --write-if-changed -o lib/Target/AArch64/AArch64GenDisassemblerTables.inc -d lib/Target/AArch64/AArch64GenDisassemblerTables.inc.d
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0  llvm-tblgen     0x000055e201e003d8
1  llvm-tblgen     0x000055e201dfdc75
2  libpthread.so.0 0x00007f980d01a140
3  libc.so.6       0x00007f980cb3ad51 gsignal + 321
4  libc.so.6       0x00007f980cb24537 abort + 291
5  libc.so.6       0x00007f980cb2440f
6  libc.so.6       0x00007f980cb336d2
7  llvm-tblgen     0x000055e201c7652e
8  llvm-tblgen     0x000055e201c82099
9  llvm-tblgen     0x000055e201c81c34
10 llvm-tblgen     0x000055e201c83403
11 llvm-tblgen     0x000055e201c97cbe
12 llvm-tblgen     0x000055e201e3beeb
13 llvm-tblgen     0x000055e201e0b2a0
14 llvm-tblgen     0x000055e201ae967f
15 libc.so.6       0x00007f980cb25d7a __libc_start_main + 234
16 llvm-tblgen     0x000055e201ab1cba
Aborted
14.386 [2567/63/1231] Building MSP430GenDisassemblerTables.inc...
14.405 [2567/62/1232] Building VEGenDAGISel.inc...
14.552 [2567/61/1233] Building AVRGenRegisterInfo.inc...
14.594 [2567/60/1234] Building AVRGenMCCodeEmitter.inc...
14.630 [2567/59/1235] Building AArch64GenAsmWriter1.inc...
14.661 [2567/58/1236] Building ARMGenDisassemblerTables.inc...
14.708 [2567/57/1237] Building ARMGenRegisterInfo.inc...
14.779 [2567/56/1238] Building MSP430GenDAGISel.inc...
14.794 [2567/55/1239] Building ARMGenAsmMatcher.inc...
14.839 [2567/54/1240] Building AVRGenDAGISel.inc...
14.853 [2567/53/1241] Building ARMGenMCCodeEmitter.inc...
14.856 [2567/52/1242] Building ARMGenSystemRegister.inc...
14.971 [2567/51/1243] Building AArch64GenRegisterBank.inc...
15.030 [2567/50/1244] Building AVRGenSubtargetInfo.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/135882