[llvm] [AArch64] Generalize integer FPR lane stores for all types (PR #134117)

[Paul Walker via llvm-commits]

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@@ -24025,6 +24025,13 @@ static SDValue performSTORECombine(SDNode *N,
     EVT VectorVT = Vector.getValueType();
     EVT ElemVT = VectorVT.getVectorElementType();
 
+    // Propagate zero constants (applying this fold may miss optimizations).
+    if (ISD::isConstantSplatVectorAllZeros(Vector.getNode())) {
+      SDValue ZeroElt = DAG.getConstant(0, DL, ValueVT);
+      DAG.ReplaceAllUsesWith(Value, ZeroElt);
+      return SDValue();
+    }
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paulwalker-arm wrote:

Yep, definitely future work.  It's worth looking at `visitBITCAST` first though because I think it only affects floating point build_vectors that are bit casted to integer.  When the "redundant" bit casting is removed I believe existing combines will then take over.

https://github.com/llvm/llvm-project/pull/134117