[llvm] [RISCV] Add TuneNoDefaultUnroll to generic CPUs (PR #135318)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Mon Apr 14 04:42:01 PDT 2025


https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/135318

>From af8e955ef862a3701f69b603e16bfead5c34d236 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Fri, 11 Apr 2025 11:51:50 +0800
Subject: [PATCH 1/2] [RISCV] Add TuneNoDefaultUnroll to generic CPUs

Almost all CPUs have added this.

We may enable it by default and remove this feature.

Fixes #134272.
---
 llvm/lib/Target/RISCV/RISCVProcessors.td | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 9d48adeec5e86..07a938db3e258 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -86,7 +86,8 @@ class RISCVTuneProcessorModel<string n,
                               list<SubtargetFeature> f = []>
     : ProcessorModel<n, m, f,tunef>;
 
-defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
+defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore,
+                              TuneNoDefaultUnroll];
 
 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
                                        NoSchedModel,

>From 26779537886b9498743504ab7b82e7539ff05eec Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Mon, 14 Apr 2025 19:41:49 +0800
Subject: [PATCH 2/2] Set DefaultUnrollRuntimeCount to 4 for in-oder

---
 llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 9b91de36a688a..d4e533bc143c1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2565,6 +2565,10 @@ void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
   // taken cost of the backedge.
   if (Cost < 12)
     UP.Force = true;
+
+  // Set a lower runtime unrolling count for in-order models.
+  if (!ST->getSchedModel().isOutOfOrder())
+    UP.DefaultUnrollRuntimeCount = 4;
 }
 
 void RISCVTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,



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