[llvm] Address Codegen bug related to marking subregister MachineOperand defines as undef (PR #134929)

[Matt Arsenault via llvm-commits]

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@@ -3979,6 +3979,32 @@ void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
       continue;
     LLVM_DEBUG(dbgs() << "  Rescheduling physreg copy ";
                DAG->dumpNode(*Dep.getSUnit()));
+
+    // Check to make sure that there are no subreg defintions of the given
+    // register between it's new and old location that are marked as undef. If
+    // so, mark the current instruction as undef instead.
+    SmallVector<MachineOperand *, 1> SubregDefs;
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arsenm wrote:

Shouldn't need to accumulate this set 

https://github.com/llvm/llvm-project/pull/134929