[llvm] [AArch64] Generalize integer FPR lane stores for all types (PR #134117)

[Benjamin Maxwell via llvm-commits]

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@@ -232,7 +231,7 @@ define void @v2i16(ptr %p1, ptr %p2) {
 ; CHECK-SD-NEXT:    ld1 { v0.h }[2], [x8]
 ; CHECK-SD-NEXT:    ld1 { v1.h }[2], [x9]
 ; CHECK-SD-NEXT:    add v0.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT:    mov s1, v0.s[1]
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MacDue wrote:

This didn't exist in the previous fold (which extracted an FPR), but is an artifact of inserting into a vector and then extracting the scalar FPR as a sub register. 

I'll see if it can be avoided while keeping the DAG combine generic enough to handle `i8` stores. 

https://github.com/llvm/llvm-project/pull/134117