[llvm] [CodeGen] Simplify expandRoundInexactToOdd (PR #134988)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 9 03:31:40 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
FP_ROUND and FP_EXTEND the input value before FABSing it. This avoids
some bit twiddling to copy the sign bit from the input to the result. It
does introduce one extra FABS, but that is folded into another
instruction for free on AMDGPU, which is the only target currently
affected by this change.
---
Patch is 72.45 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/134988.diff
4 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+7-25)
- (modified) llvm/test/CodeGen/AMDGPU/bf16-conversions.ll (+86-112)
- (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+46-52)
- (modified) llvm/test/CodeGen/AMDGPU/fp_trunc_store_fp64_to_bf16.ll (+342-382)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 0f38bbd46cbca..89f806d8b1c30 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -11608,28 +11608,13 @@ SDValue TargetLowering::expandRoundInexactToOdd(EVT ResultVT, SDValue Op,
// correct for this using a trick explained in: Boldo, Sylvie, and
// Guillaume Melquiond. "When double rounding is odd." 17th IMACS
// World Congress. 2005.
- unsigned BitSize = OperandVT.getScalarSizeInBits();
- EVT WideIntVT = OperandVT.changeTypeToInteger();
- SDValue OpAsInt = DAG.getBitcast(WideIntVT, Op);
- SDValue SignBit =
- DAG.getNode(ISD::AND, dl, WideIntVT, OpAsInt,
- DAG.getConstant(APInt::getSignMask(BitSize), dl, WideIntVT));
- SDValue AbsWide;
- if (isOperationLegalOrCustom(ISD::FABS, OperandVT)) {
- AbsWide = DAG.getNode(ISD::FABS, dl, OperandVT, Op);
- } else {
- SDValue ClearedSign = DAG.getNode(
- ISD::AND, dl, WideIntVT, OpAsInt,
- DAG.getConstant(APInt::getSignedMaxValue(BitSize), dl, WideIntVT));
- AbsWide = DAG.getBitcast(OperandVT, ClearedSign);
- }
- SDValue AbsNarrow = DAG.getFPExtendOrRound(AbsWide, dl, ResultVT);
- SDValue AbsNarrowAsWide = DAG.getFPExtendOrRound(AbsNarrow, dl, OperandVT);
+ SDValue Narrow = DAG.getFPExtendOrRound(Op, dl, ResultVT);
+ SDValue NarrowAsWide = DAG.getFPExtendOrRound(Narrow, dl, OperandVT);
// We can keep the narrow value as-is if narrowing was exact (no
// rounding error), the wide value was NaN (the narrow value is also
// NaN and should be preserved) or if we rounded to the odd value.
- SDValue NarrowBits = DAG.getNode(ISD::BITCAST, dl, ResultIntVT, AbsNarrow);
+ SDValue NarrowBits = DAG.getNode(ISD::BITCAST, dl, ResultIntVT, Narrow);
SDValue One = DAG.getConstant(1, dl, ResultIntVT);
SDValue NegativeOne = DAG.getAllOnesConstant(dl, ResultIntVT);
SDValue And = DAG.getNode(ISD::AND, dl, ResultIntVT, NarrowBits, One);
@@ -11640,13 +11625,15 @@ SDValue TargetLowering::expandRoundInexactToOdd(EVT ResultVT, SDValue Op,
SDValue AlreadyOdd = DAG.getSetCC(dl, ResultIntVTCCVT, And, Zero, ISD::SETNE);
EVT WideSetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
- AbsWide.getValueType());
+ Op.getValueType());
// We keep results which are exact, odd or NaN.
SDValue KeepNarrow =
- DAG.getSetCC(dl, WideSetCCVT, AbsWide, AbsNarrowAsWide, ISD::SETUEQ);
+ DAG.getSetCC(dl, WideSetCCVT, Op, NarrowAsWide, ISD::SETUEQ);
KeepNarrow = DAG.getNode(ISD::OR, dl, WideSetCCVT, KeepNarrow, AlreadyOdd);
// We morally performed a round-down if AbsNarrow is smaller than
// AbsWide.
+ SDValue AbsWide = DAG.getNode(ISD::FABS, dl, OperandVT, Op);
+ SDValue AbsNarrowAsWide = DAG.getNode(ISD::FABS, dl, OperandVT, NarrowAsWide);
SDValue NarrowIsRd =
DAG.getSetCC(dl, WideSetCCVT, AbsWide, AbsNarrowAsWide, ISD::SETOGT);
// If the narrow value is odd or exact, pick it.
@@ -11656,11 +11643,6 @@ SDValue TargetLowering::expandRoundInexactToOdd(EVT ResultVT, SDValue Op,
SDValue Adjust = DAG.getSelect(dl, ResultIntVT, NarrowIsRd, One, NegativeOne);
SDValue Adjusted = DAG.getNode(ISD::ADD, dl, ResultIntVT, NarrowBits, Adjust);
Op = DAG.getSelect(dl, ResultIntVT, KeepNarrow, NarrowBits, Adjusted);
- int ShiftAmount = BitSize - ResultVT.getScalarSizeInBits();
- SDValue ShiftCnst = DAG.getShiftAmountConstant(ShiftAmount, WideIntVT, dl);
- SignBit = DAG.getNode(ISD::SRL, dl, WideIntVT, SignBit, ShiftCnst);
- SignBit = DAG.getNode(ISD::TRUNCATE, dl, ResultIntVT, SignBit);
- Op = DAG.getNode(ISD::OR, dl, ResultIntVT, Op, SignBit);
return DAG.getNode(ISD::BITCAST, dl, ResultVT, Op);
}
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index 3be911ab9e7f4..a597faa028f22 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -111,75 +111,65 @@ define amdgpu_ps float @v_test_cvt_f32_bf16_v(float %src) {
define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
; GFX-942-LABEL: v_test_cvt_v2f64_v2bf16_v:
; GFX-942: ; %bb.0:
-; GFX-942-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
+; GFX-942-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
-; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
-; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-942-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
+; GFX-942-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
-; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
+; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX-942-NEXT: s_brev_b32 s4, 1
-; GFX-942-NEXT: v_and_or_b32 v5, v1, s4, v4
-; GFX-942-NEXT: v_bfe_u32 v4, v4, 16, 1
-; GFX-942-NEXT: s_movk_i32 s5, 0x7fff
-; GFX-942-NEXT: v_add3_u32 v4, v4, v5, s5
-; GFX-942-NEXT: v_or_b32_e32 v5, 0x400000, v5
+; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX-942-NEXT: s_movk_i32 s4, 0x7fff
+; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s4
+; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
; GFX-942-NEXT: s_nop 1
-; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX-942-NEXT: v_cvt_f32_f64_e64 v5, |v[2:3]|
+; GFX-942-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
+; GFX-942-NEXT: v_cvt_f32_f64_e32 v5, v[2:3]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[0:1], v5
; GFX-942-NEXT: v_and_b32_e32 v6, 1, v5
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, v[0:1]
-; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[2:3]|, v[0:1]
-; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, |v[0:1]|
+; GFX-942-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[0:1]
+; GFX-942-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v6
; GFX-942-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v0, v5, v0
-; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
+; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-942-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
-; GFX-942-NEXT: v_and_or_b32 v1, v3, s4, v0
-; GFX-942-NEXT: v_bfe_u32 v0, v0, 16, 1
-; GFX-942-NEXT: v_add3_u32 v0, v0, v1, s5
-; GFX-942-NEXT: v_or_b32_e32 v1, 0x400000, v1
+; GFX-942-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX-942-NEXT: v_add3_u32 v1, v1, v0, s4
+; GFX-942-NEXT: v_or_b32_e32 v0, 0x400000, v0
; GFX-942-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[2:3]
; GFX-942-NEXT: s_mov_b32 s0, 0x7060302
; GFX-942-NEXT: s_nop 0
-; GFX-942-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX-942-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX-942-NEXT: v_perm_b32 v0, v0, v4, s0
; GFX-942-NEXT: ; return to shader part epilog
;
; GFX-950-LABEL: v_test_cvt_v2f64_v2bf16_v:
; GFX-950: ; %bb.0:
-; GFX-950-NEXT: v_mov_b32_e32 v4, v3
-; GFX-950-NEXT: v_and_b32_e32 v3, 0x7fffffff, v4
-; GFX-950-NEXT: v_mov_b32_e32 v5, v1
-; GFX-950-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
-; GFX-950-NEXT: v_cvt_f64_f32_e32 v[6:7], v1
-; GFX-950-NEXT: v_and_b32_e32 v8, 1, v1
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], v[2:3], v[6:7]
-; GFX-950-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[6:7]
-; GFX-950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v8
+; GFX-950-NEXT: v_cvt_f32_f64_e32 v6, v[2:3]
+; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
+; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, |v[4:5]|
+; GFX-950-NEXT: v_cmp_nlg_f64_e32 vcc, v[2:3], v[4:5]
+; GFX-950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
; GFX-950-NEXT: v_cndmask_b32_e64 v2, -1, 1, s[2:3]
-; GFX-950-NEXT: v_add_u32_e32 v2, v1, v2
+; GFX-950-NEXT: v_add_u32_e32 v2, v6, v2
; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
-; GFX-950-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX-950-NEXT: s_brev_b32 s4, 1
-; GFX-950-NEXT: v_and_or_b32 v4, v4, s4, v1
-; GFX-950-NEXT: v_and_b32_e32 v1, 0x7fffffff, v5
-; GFX-950-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
-; GFX-950-NEXT: v_cvt_f64_f32_e32 v[2:3], v6
-; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], v[0:1], v[2:3]
+; GFX-950-NEXT: v_cvt_f32_f64_e32 v5, v[0:1]
+; GFX-950-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
+; GFX-950-NEXT: v_cvt_f64_f32_e32 v[2:3], v5
+; GFX-950-NEXT: v_and_b32_e32 v6, 1, v5
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
; GFX-950-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[2:3]
-; GFX-950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
+; GFX-950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v6
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
-; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
+; GFX-950-NEXT: v_add_u32_e32 v0, v5, v0
; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
-; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX-950-NEXT: v_and_or_b32 v0, v5, s4, v0
+; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, v4
; GFX-950-NEXT: ; return to shader part epilog
%res = fptrunc <2 x double> %src to <2 x bfloat>
@@ -348,42 +338,38 @@ entry:
define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f64_to_bf16:
; GFX-942: ; %bb.0: ; %entry
-; GFX-942-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
+; GFX-942-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
-; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
-; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-942-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
+; GFX-942-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
-; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
+; GFX-942-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX-942-NEXT: s_brev_b32 s0, 1
-; GFX-942-NEXT: v_and_or_b32 v5, v1, s0, v4
-; GFX-942-NEXT: v_bfe_u32 v4, v4, 16, 1
+; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
-; GFX-942-NEXT: v_add3_u32 v4, v4, v5, s0
-; GFX-942-NEXT: v_or_b32_e32 v5, 0x400000, v5
+; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
+; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
; GFX-942-NEXT: s_nop 1
-; GFX-942-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; GFX-942-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX-942-NEXT: flat_store_short_d16_hi v[2:3], v0
; GFX-942-NEXT: s_endpgm
;
; GFX-950-LABEL: fptrunc_f64_to_bf16:
; GFX-950: ; %bb.0: ; %entry
-; GFX-950-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
+; GFX-950-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
-; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
-; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-950-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
+; GFX-950-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v7
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
-; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
+; GFX-950-NEXT: s_or_b64 vcc, vcc, s[0:1]
; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
-; GFX-950-NEXT: s_brev_b32 s0, 1
-; GFX-950-NEXT: v_and_or_b32 v0, v1, s0, v0
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
@@ -396,44 +382,38 @@ entry:
define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f64_to_bf16_neg:
; GFX-942: ; %bb.0: ; %entry
-; GFX-942-NEXT: v_cvt_f32_f64_e64 v7, |v[0:1]|
-; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v7
-; GFX-942-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
-; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
-; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX-942-NEXT: v_cvt_f32_f64_e64 v6, -v[0:1]
+; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
+; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], -v[0:1], v[4:5]
+; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
-; GFX-942-NEXT: v_add_u32_e32 v4, v7, v4
+; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
-; GFX-942-NEXT: s_brev_b32 s4, 1
-; GFX-942-NEXT: v_xor_b32_e32 v6, 0x80000000, v1
-; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX-942-NEXT: v_and_or_b32 v5, v6, s4, v4
-; GFX-942-NEXT: v_bfe_u32 v4, v4, 16, 1
+; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
-; GFX-942-NEXT: v_add3_u32 v4, v4, v5, s0
-; GFX-942-NEXT: v_or_b32_e32 v5, 0x400000, v5
+; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
+; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]
; GFX-942-NEXT: s_nop 1
-; GFX-942-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; GFX-942-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX-942-NEXT: flat_store_short_d16_hi v[2:3], v0
; GFX-942-NEXT: s_endpgm
;
; GFX-950-LABEL: fptrunc_f64_to_bf16_neg:
; GFX-950: ; %bb.0: ; %entry
-; GFX-950-NEXT: v_cvt_f32_f64_e64 v7, |v[0:1]|
-; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v7
-; GFX-950-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
-; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
-; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX-950-NEXT: v_cvt_f32_f64_e64 v6, -v[0:1]
+; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
+; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], -v[0:1], v[4:5]
+; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
-; GFX-950-NEXT: v_add_u32_e32 v0, v7, v0
+; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
-; GFX-950-NEXT: s_brev_b32 s4, 1
-; GFX-950-NEXT: v_xor_b32_e32 v6, 0x80000000, v1
-; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; GFX-950-NEXT: v_and_or_b32 v0, v6, s4, v0
+; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
@@ -447,44 +427,38 @@ entry:
define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
; GFX-942-LABEL: fptrunc_f64_to_bf16_abs:
; GFX-942: ; %bb.0: ; %entry
-; GFX-942-NEXT: v_cvt_f32_f64_e64 v7, |v[0:1]|
-; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v7
-; GFX-942-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
+; GFX-942-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
+; GFX-942-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
+; GFX-942-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX-942-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-942-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
-; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX-942-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-942-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
-; GFX-942-NEXT: v_add_u32_e32 v4, v7, v4
+; GFX-942-NEXT: v_add_u32_e32 v4, v6, v4
; GFX-942-NEXT: s_or_b64 vcc, s[0:1], vcc
-; GFX-942-NEXT: v_and_b32_e32 v6, 0x7fffffff, v1
-; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX-942-NEXT: s_brev_b32 s0, 1
-; GFX-942-NEXT: v_and_or_b32 v5, v6, s0, v4
-; GFX-942-NEXT: v_bfe_u32 v4, v4, 16, 1
+; GFX-942-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX-942-NEXT: v_bfe_u32 v5, v4, 16, 1
; GFX-942-NEXT: s_movk_i32 s0, 0x7fff
-; GFX-942-NEXT: v_add3_u32 v4, v4, v5, s0
-; GFX-942-NEXT: v_or_b32_e32 v5, 0x400000, v5
+; GFX-942-NEXT: v_add3_u32 v5, v5, v4, s0
+; GFX-942-NEXT: v_or_b32_e32 v4, 0x400000, v4
; GFX-942-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, |v[0:1]|
; GFX-942-NEXT: s_nop 1
-; GFX-942-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; GFX-942-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX-942-NEXT: flat_store_short_d16_hi v[2:3], v0
; GFX-942-NEXT: s_endpgm
;
; GFX-950-LABEL: fptrunc_f64_to_bf16_abs:
; GFX-950: ; %bb.0: ; %entry
-; GFX-950-NEXT: v_cvt_f32_f64_e64 v7, |v[0:1]|
-; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v7
-; GFX-950-NEXT: v_and_b32_e32 v8, 1, v7
-; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
+; GFX-950-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
+; GFX-950-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
+; GFX-950-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX-950-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
; GFX-950-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
-; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX-950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
; GFX-950-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
-; GFX-950-NEXT: v_add_u32_e32 v0, v7, v0
+; GFX-950-NEXT: v_add_u32_e32 v0, v6, v0
; GFX-950-NEXT: s_or_b64 vcc, s[0:1], vcc
-; GFX-950-NEXT: v_and_b32_e32 v6, 0x7fffffff, v1
-; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; GFX-950-NEXT: s_brev_b32 s0, 1
-; GFX-950-NEXT: v_and_or_b32 v0, v6, s0, v0
+; GFX-950-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX-950-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
; GFX-950-NEXT: flat_store_short v[2:3], v0
; GFX-950-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 8582b61bbbd82..d845cadab6f7e 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -2287,24 +2287,22 @@ define void @test_load_store_f64_to_bf16(ptr addrspace(1) %in, ptr addrspace(1)
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
-; GFX8-NEXT: v_and_b32_e32 v7, 0x80000000, v1
+; GFX8-NEXT: v_cvt_f32_f64_e32 v6, v[0:1]
; GFX8-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
-; GFX8-NEXT: v_and_b32_e32 v8, 1, v6
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
-; GFX8-NEXT: v_cmp_gt_f64_e64 s[4:5], |v[0:1]|, v[4:5]
-; GFX8-NEXT: v_cmp_nlg_f64_e64 s[6:7], |v[0:1]|, v[4:5]
-; GFX8-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[4:5]
-; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v6, v4
-; GFX8-NEXT: s_or_b64 vcc, s[6:7], vcc
+; GFX8-NEXT: v_and_b32_e32 v7, 1, v6
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v7
+; GFX8-NEXT: v_cmp_gt_f64_e64 s[6:7], |v[0:1]|, |v[4:5]|
+; GFX8-NEXT: v_cmp_nlg_f64_e32 vcc, v[0:1], v[4:5]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[6:7]
+; GFX8-NEXT: v_add_u32_e64 v4, s[6:7], v6, v4
+; GFX8-NEXT: s_or_b64 vcc, vcc, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT: v_or_b32_e32 v5, v4, v7
-; GFX8-NEXT: v_bfe_u32 v4, v4, 16, 1
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
+; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX8-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
; GFX8-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
-; GFX8-NEXT: v_or_b32_e32 v5, 0x400000, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: flat_store_short v[2:3], v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
@@ -2314,25 +2312,23 @@ define...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/134988
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