[llvm] [MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (PR #132704)

[Mallikarjuna Gouda via llvm-commits]

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+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=mips64el -mcpu=i6400 --mattr=msa -timeline -iterations=1 < %s | FileCheck %s
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mgoudar wrote:

i6400 and i6500 comes with MSA implemented and enabled by default, user can disable MSA with reset bit from the software. I think I need to enable FeatureMSA as part of i6400/i6500 cpu definition. I shall create  a separate PR for that and share here.

https://github.com/llvm/llvm-project/pull/132704