[llvm] [WIP] Separate Asan instrumentation in amdgpu-sw-lower-lds. (PR #134832)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 8 03:33:54 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Chaitanya (skc7)
<details>
<summary>Changes</summary>
---
Patch is 203.62 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/134832.diff
28 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp (+61-31)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll (+54-54)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access.ll (+23-36)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll (+24-23)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test.ll (+19-26)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll (+83-83)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll (+33-58)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll (+23-22)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return.ll (+27-41)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll (+54-54)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll (+23-36)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll (+48-47)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test.ll (+19-32)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll (+34-33)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param.ll (+22-33)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll (+9-14)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll (+32-75)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll (+10-31)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll (+10-31)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-O0.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll (+38-38)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll (+30-30)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll (+54-54)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test.ll (+17-31)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll (+5-20)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
index cc0d374c99254..4a4b9e97648f9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
@@ -353,9 +353,11 @@ void AMDGPUSwLowerLDS::buildSwLDSGlobal(Function *Func) {
M, IRB.getPtrTy(), false, GlobalValue::InternalLinkage,
PoisonValue::get(IRB.getPtrTy()), "llvm.amdgcn.sw.lds." + Func->getName(),
nullptr, GlobalValue::NotThreadLocal, AMDGPUAS::LOCAL_ADDRESS, false);
- GlobalValue::SanitizerMetadata MD;
- MD.NoAddress = true;
- LDSParams.SwLDS->setSanitizerMetadata(MD);
+ if (AsanInstrumentLDS) {
+ GlobalValue::SanitizerMetadata MD;
+ MD.NoAddress = true;
+ LDSParams.SwLDS->setSanitizerMetadata(MD);
+ }
}
void AMDGPUSwLowerLDS::buildSwDynLDSGlobal(Function *Func) {
@@ -371,9 +373,11 @@ void AMDGPUSwLowerLDS::buildSwDynLDSGlobal(Function *Func) {
"llvm.amdgcn." + Func->getName() + ".dynlds", nullptr,
GlobalValue::NotThreadLocal, AMDGPUAS::LOCAL_ADDRESS, false);
markUsedByKernel(Func, LDSParams.SwDynLDS);
- GlobalValue::SanitizerMetadata MD;
- MD.NoAddress = true;
- LDSParams.SwDynLDS->setSanitizerMetadata(MD);
+ if (AsanInstrumentLDS) {
+ GlobalValue::SanitizerMetadata MD;
+ MD.NoAddress = true;
+ LDSParams.SwDynLDS->setSanitizerMetadata(MD);
+ }
}
void AMDGPUSwLowerLDS::populateSwLDSAttributeAndMetadata(Function *Func) {
@@ -436,8 +440,8 @@ void AMDGPUSwLowerLDS::populateSwMetadataGlobal(Function *Func) {
Constant *ItemStartOffset = ConstantInt::get(Int32Ty, MallocSize);
Constant *SizeInBytesConst = ConstantInt::get(Int32Ty, SizeInBytes);
// Get redzone size corresponding a size.
- const uint64_t RightRedzoneSize =
- AMDGPU::getRedzoneSizeForGlobal(AsanScale, SizeInBytes);
+ const uint64_t RightRedzoneSize = AsanInstrumentLDS ?
+ AMDGPU::getRedzoneSizeForGlobal(AsanScale, SizeInBytes) : 0;
// Update MallocSize with current size and redzone size.
MallocSize += SizeInBytes;
if (!AMDGPU::isDynamicLDS(*GV))
@@ -489,9 +493,11 @@ void AMDGPUSwLowerLDS::populateSwMetadataGlobal(Function *Func) {
LDSParams.SwLDS->setAlignment(MaxAlignment);
if (LDSParams.SwDynLDS)
LDSParams.SwDynLDS->setAlignment(MaxAlignment);
- GlobalValue::SanitizerMetadata MD;
- MD.NoAddress = true;
- LDSParams.SwLDSMetadata->setSanitizerMetadata(MD);
+ if (AsanInstrumentLDS) {
+ GlobalValue::SanitizerMetadata MD;
+ MD.NoAddress = true;
+ LDSParams.SwLDSMetadata->setSanitizerMetadata(MD);
+ }
}
void AMDGPUSwLowerLDS::populateLDSToReplacementIndicesMap(Function *Func) {
@@ -869,22 +875,34 @@ void AMDGPUSwLowerLDS::lowerKernelLDSAccesses(Function *Func,
// Create a call to malloc function which does device global memory allocation
// with size equals to all LDS global accesses size in this kernel.
- Value *ReturnAddress =
- IRB.CreateIntrinsic(Intrinsic::returnaddress, {IRB.getInt32(0)});
- FunctionCallee MallocFunc = M.getOrInsertFunction(
+ Value *MallocPtr;
+ if (AsanInstrumentLDS) {
+ Value *ReturnAddress =
+ IRB.CreateIntrinsic(Intrinsic::returnaddress, {}, {IRB.getInt32(0)});
+ FunctionCallee MallocFunc = M.getOrInsertFunction(
StringRef("__asan_malloc_impl"),
FunctionType::get(Int64Ty, {Int64Ty, Int64Ty}, false));
- Value *RAPtrToInt = IRB.CreatePtrToInt(ReturnAddress, Int64Ty);
- Value *MallocCall = IRB.CreateCall(MallocFunc, {CurrMallocSize, RAPtrToInt});
-
- Value *MallocPtr =
+ Value *RAPtrToInt = IRB.CreatePtrToInt(ReturnAddress, Int64Ty);
+ Value *MallocCall = IRB.CreateCall(MallocFunc, {CurrMallocSize, RAPtrToInt});
+ MallocPtr =
+ IRB.CreateIntToPtr(MallocCall, IRB.getPtrTy(AMDGPUAS::GLOBAL_ADDRESS));
+ }
+ else {
+ Type *PtrTy = IRB.getPtrTy(AMDGPUAS::GLOBAL_ADDRESS);
+ FunctionCallee MallocFunc = M.getOrInsertFunction(
+ StringRef("__ockl_dm_alloc"),
+ FunctionType::get(PtrTy, {Int64Ty}, false));
+ Value *MallocCall = IRB.CreateCall(MallocFunc, {CurrMallocSize});
+ MallocPtr =
IRB.CreateIntToPtr(MallocCall, IRB.getPtrTy(AMDGPUAS::GLOBAL_ADDRESS));
+ }
// Create store of malloc to new global
IRB.CreateStore(MallocPtr, SwLDS);
// Create calls to __asan_poison_region to poison redzones.
- poisonRedzones(Func, MallocPtr);
+ if (AsanInstrumentLDS)
+ poisonRedzones(Func, MallocPtr);
// Create branch to PrevEntryBlock
IRB.CreateBr(PrevEntryBlock);
@@ -932,14 +950,22 @@ void AMDGPUSwLowerLDS::lowerKernelLDSAccesses(Function *Func,
IRB.SetInsertPoint(FreeBlock, FreeBlock->begin());
// Free the previously allocate device global memory.
- FunctionCallee AsanFreeFunc = M.getOrInsertFunction(
+ Value *MallocPtrToInt = IRB.CreatePtrToInt(LoadMallocPtr, Int64Ty);
+ if (AsanInstrumentLDS) {
+ FunctionCallee AsanFreeFunc = M.getOrInsertFunction(
StringRef("__asan_free_impl"),
FunctionType::get(IRB.getVoidTy(), {Int64Ty, Int64Ty}, false));
- Value *ReturnAddr =
- IRB.CreateIntrinsic(Intrinsic::returnaddress, IRB.getInt32(0));
- Value *RAPToInt = IRB.CreatePtrToInt(ReturnAddr, Int64Ty);
- Value *MallocPtrToInt = IRB.CreatePtrToInt(LoadMallocPtr, Int64Ty);
- IRB.CreateCall(AsanFreeFunc, {MallocPtrToInt, RAPToInt});
+ Value *ReturnAddr =
+ IRB.CreateIntrinsic(Intrinsic::returnaddress, {}, IRB.getInt32(0));
+ Value *RAPToInt = IRB.CreatePtrToInt(ReturnAddr, Int64Ty);
+ IRB.CreateCall(AsanFreeFunc, {MallocPtrToInt, RAPToInt});
+ }
+ else {
+ FunctionCallee FreeFunc = M.getOrInsertFunction(
+ StringRef("__ockl_dm_dealloc"),
+ FunctionType::get(IRB.getVoidTy(), {Int64Ty}, false));
+ IRB.CreateCall(FreeFunc, {MallocPtrToInt});
+ }
IRB.CreateBr(EndBlock);
@@ -1013,9 +1039,11 @@ void AMDGPUSwLowerLDS::buildNonKernelLDSBaseTable(
M, AllKernelsOffsetsType, true, GlobalValue::InternalLinkage, init,
"llvm.amdgcn.sw.lds.base.table", nullptr, GlobalValue::NotThreadLocal,
AMDGPUAS::GLOBAL_ADDRESS);
- GlobalValue::SanitizerMetadata MD;
- MD.NoAddress = true;
- NKLDSParams.LDSBaseTable->setSanitizerMetadata(MD);
+ if (AsanInstrumentLDS) {
+ GlobalValue::SanitizerMetadata MD;
+ MD.NoAddress = true;
+ NKLDSParams.LDSBaseTable->setSanitizerMetadata(MD);
+ }
}
void AMDGPUSwLowerLDS::buildNonKernelLDSOffsetTable(
@@ -1051,9 +1079,11 @@ void AMDGPUSwLowerLDS::buildNonKernelLDSOffsetTable(
M, AllKernelsOffsetsType, true, GlobalValue::InternalLinkage, Init,
"llvm.amdgcn.sw.lds.offset.table", nullptr, GlobalValue::NotThreadLocal,
AMDGPUAS::GLOBAL_ADDRESS);
- GlobalValue::SanitizerMetadata MD;
- MD.NoAddress = true;
- NKLDSParams.LDSOffsetTable->setSanitizerMetadata(MD);
+ if (AsanInstrumentLDS) {
+ GlobalValue::SanitizerMetadata MD;
+ MD.NoAddress = true;
+ NKLDSParams.LDSOffsetTable->setSanitizerMetadata(MD);
+ }
}
void AMDGPUSwLowerLDS::lowerNonKernelLDSAccesses(
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
index 2776b9187724c..f81d1bb3c2591 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access-asan.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 4
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 5
; RUN: opt < %s -passes=amdgpu-sw-lower-lds -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s
; Test to check indirect dynamic LDS access through a non-kernel from kernel is lowered correctly.
@@ -43,16 +43,16 @@ define void @use_variables() sanitize_address {
; CHECK-NEXT: [[TMP24:%.*]] = and i1 [[TMP20]], [[TMP23]]
; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP24]])
; CHECK-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP25]], 0
-; CHECK-NEXT: br i1 [[TMP26]], label [[ASAN_REPORT:%.*]], label [[TMP29:%.*]], !prof [[PROF3:![0-9]+]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP24]], label [[TMP27:%.*]], label [[TMP28:%.*]]
-; CHECK: 27:
+; CHECK-NEXT: br i1 [[TMP26]], label %[[ASAN_REPORT:.*]], label %[[BB29:.*]], !prof [[PROF3:![0-9]+]]
+; CHECK: [[ASAN_REPORT]]:
+; CHECK-NEXT: br i1 [[TMP24]], label %[[BB27:.*]], label %[[BB28:.*]]
+; CHECK: [[BB27]]:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP47]]) #[[ATTR7:[0-9]+]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP28]]
-; CHECK: 28:
-; CHECK-NEXT: br label [[TMP29]]
-; CHECK: 29:
+; CHECK-NEXT: br label %[[BB28]]
+; CHECK: [[BB28]]:
+; CHECK-NEXT: br label %[[BB29]]
+; CHECK: [[BB29]]:
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP14]], align 4
; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP15]] to i32
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP7]], i32 [[TMP30]]
@@ -68,16 +68,16 @@ define void @use_variables() sanitize_address {
; CHECK-NEXT: [[TMP41:%.*]] = and i1 [[TMP37]], [[TMP40]]
; CHECK-NEXT: [[TMP42:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP41]])
; CHECK-NEXT: [[TMP43:%.*]] = icmp ne i64 [[TMP42]], 0
-; CHECK-NEXT: br i1 [[TMP43]], label [[ASAN_REPORT1:%.*]], label [[TMP46:%.*]], !prof [[PROF3]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP41]], label [[TMP44:%.*]], label [[TMP45:%.*]]
-; CHECK: 44:
+; CHECK-NEXT: br i1 [[TMP43]], label %[[ASAN_REPORT1:.*]], label %[[BB46:.*]], !prof [[PROF3]]
+; CHECK: [[ASAN_REPORT1]]:
+; CHECK-NEXT: br i1 [[TMP41]], label %[[BB44:.*]], label %[[BB45:.*]]
+; CHECK: [[BB44]]:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP32]]) #[[ATTR7]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP45]]
-; CHECK: 45:
-; CHECK-NEXT: br label [[TMP46]]
-; CHECK: 46:
+; CHECK-NEXT: br label %[[BB45]]
+; CHECK: [[BB45]]:
+; CHECK-NEXT: br label %[[BB46]]
+; CHECK: [[BB46]]:
; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP31]], align 8
; CHECK-NEXT: ret void
;
@@ -89,15 +89,15 @@ define void @use_variables() sanitize_address {
define amdgpu_kernel void @k0() sanitize_address {
; CHECK-LABEL: define amdgpu_kernel void @k0(
; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META4:![0-9]+]] {
-; CHECK-NEXT: WId:
+; CHECK-NEXT: [[WID:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
-; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP21:%.*]]
-; CHECK: Malloc:
+; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB32:.*]]
+; CHECK: [[MALLOC]]:
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]
@@ -134,9 +134,9 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP74:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP20]], i64 68
; CHECK-NEXT: [[TMP75:%.*]] = ptrtoint ptr addrspace(1) [[TMP74]] to i64
; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP75]], i64 28)
-; CHECK-NEXT: br label [[TMP21]]
-; CHECK: 32:
-; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, [[WID:%.*]] ], [ true, [[MALLOC]] ]
+; CHECK-NEXT: br label %[[BB32]]
+; CHECK: [[BB32]]:
+; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, %[[WID]] ], [ true, %[[MALLOC]] ]
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
; CHECK-NEXT: [[TMP31:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
; CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
@@ -159,16 +159,16 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP49:%.*]] = and i1 [[TMP45]], [[TMP48]]
; CHECK-NEXT: [[TMP50:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP49]])
; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i64 [[TMP50]], 0
-; CHECK-NEXT: br i1 [[TMP51]], label [[ASAN_REPORT:%.*]], label [[TMP54:%.*]], !prof [[PROF3]]
-; CHECK: asan.report:
-; CHECK-NEXT: br i1 [[TMP49]], label [[TMP52:%.*]], label [[CONDFREE:%.*]]
-; CHECK: 52:
+; CHECK-NEXT: br i1 [[TMP51]], label %[[ASAN_REPORT:.*]], label %[[BB54:.*]], !prof [[PROF3]]
+; CHECK: [[ASAN_REPORT]]:
+; CHECK-NEXT: br i1 [[TMP49]], label %[[BB52:.*]], label %[[BB53:.*]]
+; CHECK: [[BB52]]:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP40]]) #[[ATTR7]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[CONDFREE]]
-; CHECK: 53:
-; CHECK-NEXT: br label [[TMP54]]
-; CHECK: 54:
+; CHECK-NEXT: br label %[[BB53]]
+; CHECK: [[BB53]]:
+; CHECK-NEXT: br label %[[BB54]]
+; CHECK: [[BB54]]:
; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP39]], align 1
; CHECK-NEXT: [[TMP55:%.*]] = ptrtoint ptr addrspace(3) [[TMP30]] to i32
; CHECK-NEXT: [[TMP56:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP31]], i32 [[TMP55]]
@@ -187,16 +187,16 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP67:%.*]] = and i1 [[TMP62]], [[TMP66]]
; CHECK-NEXT: [[TMP68:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP67]])
; CHECK-NEXT: [[TMP69:%.*]] = icmp ne i64 [[TMP68]], 0
-; CHECK-NEXT: br i1 [[TMP69]], label [[ASAN_REPORT1:%.*]], label [[TMP72:%.*]], !prof [[PROF3]]
-; CHECK: asan.report1:
-; CHECK-NEXT: br i1 [[TMP67]], label [[TMP70:%.*]], label [[TMP71:%.*]]
-; CHECK: 72:
+; CHECK-NEXT: br i1 [[TMP69]], label %[[ASAN_REPORT1:.*]], label %[[BB74:.*]], !prof [[PROF3]]
+; CHECK: [[ASAN_REPORT1]]:
+; CHECK-NEXT: br i1 [[TMP67]], label %[[BB72:.*]], label %[[BB73:.*]]
+; CHECK: [[BB72]]:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP91]]) #[[ATTR7]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP71]]
-; CHECK: 73:
-; CHECK-NEXT: br label [[TMP72]]
-; CHECK: 74:
+; CHECK-NEXT: br label %[[BB73]]
+; CHECK: [[BB73]]:
+; CHECK-NEXT: br label %[[BB74]]
+; CHECK: [[BB74]]:
; CHECK-NEXT: [[TMP92:%.*]] = ptrtoint ptr addrspace(1) [[TMP90]] to i64
; CHECK-NEXT: [[TMP76:%.*]] = lshr i64 [[TMP92]], 3
; CHECK-NEXT: [[TMP77:%.*]] = add i64 [[TMP76]], 2147450880
@@ -209,28 +209,28 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP84:%.*]] = and i1 [[TMP80]], [[TMP83]]
; CHECK-NEXT: [[TMP85:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP84]])
; CHECK-NEXT: [[TMP86:%.*]] = icmp ne i64 [[TMP85]], 0
-; CHECK-NEXT: br i1 [[TMP86]], label [[ASAN_REPORT2:%.*]], label [[TMP89:%.*]], !prof [[PROF3]]
-; CHECK: asan.report2:
-; CHECK-NEXT: br i1 [[TMP84]], label [[TMP87:%.*]], label [[TMP88:%.*]]
-; CHECK: 87:
+; CHECK-NEXT: br i1 [[TMP86]], label %[[ASAN_REPORT2:.*]], label %[[BB89:.*]], !prof [[PROF3]]
+; CHECK: [[ASAN_REPORT2]]:
+; CHECK-NEXT: br i1 [[TMP84]], label %[[BB87:.*]], label %[[BB88:.*]]
+; CHECK: [[BB87]]:
; CHECK-NEXT: call void @__asan_report_store1(i64 [[TMP92]]) #[[ATTR7]]
; CHECK-NEXT: call void @llvm.amdgcn.unreachable()
-; CHECK-NEXT: br label [[TMP88]]
-; CHECK: 88:
-; CHECK-NEXT: br label [[TMP89]]
-; CHECK: 89:
+; CHECK-NEXT: br label %[[BB88]]
+; CHECK: [[BB88]]:
+; CHECK-NEXT: br label %[[BB89]]
+; CHECK: [[BB89]]:
; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP56]], align 2
-; CHECK-NEXT: br label [[CONDFREE1:%.*]]
-; CHECK: CondFree:
+; CHECK-NEXT: br label %[[CONDFREE:.*]]
+; CHECK: [[CONDFREE]]:
; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
-; CHECK-NEXT: br i1 [[XYZCOND]], label [[FREE:%.*]], label [[END:%.*]]
-; CHECK: Free:
+; CHECK-NEXT: br i1 [[XYZCOND]], label %[[FREE:.*]], label %[[END:.*]]
+; CHECK: [[FREE]]:
+; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr addrspace(1) [[TMP31]] to i64
; CHECK-NEXT: [[TMP32:%.*]] = call ptr @llvm.returnaddress(i32 0)
; CHECK-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP32]] to i64
-; CHECK-NEXT: [[TMP34:%.*]] = ptrtoint ptr addrspace(1) [[TMP31]] to i64
; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP34]], i64 [[TMP33]])
-; CHECK-NEXT: br label [[END]]
-; CHECK: End:
+; CHECK-NEXT: br label %[[END]]
+; CHECK: [[END]]:
; CHECK-NEXT: ret void
;
call void @use_variables()
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access.ll
index 8cbeb80d62335..7a28d60f2319c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-indirect-access.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 4
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 5
; RUN: opt < %s -passes=amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s
; Test to check indirect dynamic LDS access through a non-kernel from kernel is lowered correctly.
@@ -8,11 +8,11 @@
@lds_4 = external addrspace(3) global [0 x i8], align 8
;.
-; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]]
-; CHECK: @llvm.amdgcn.k0.dynlds = external addrspace(3) global [0 x i8], no_sanitize_address, align 8, !absolute_symbol [[META1:![0-9]+]]
-; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 64, i32 4, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 96, i32 0, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 128, i32 0, i32 32 } }, no_sanitize_address
-; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0], no_sanitize_address
-; @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [1 x [2 x ptr addrspace(1)]] [[2 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0)]], no_sanitize_address
+; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, align 8, !absolute_symbol [[META0:![0-9]+]]
+; CHECK: @llvm.amdgcn.k0.dynlds = external addrspace(3) global [0 x i8], align 8, !absolute_symbol [[META1:![0-9]+]]
+; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 8, i32 1, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 16, i32 4, i32 8 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 24, i32 0, i32 0 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 24, i32 0, i32 0 } }
+; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0]
+; @llvm.amdgcn.sw.lds.offset.table = ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/134832
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