[llvm] [AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bits=128. (PR #134068)

[Paul Walker via llvm-commits]

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@@ -2782,6 +2815,9 @@ bool AArch64LoadStoreOpt::tryToMergeIndexLdSt(MachineBasicBlock::iterator &MBBI,
 bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
                                         bool EnableNarrowZeroStOpt) {
   AArch64FunctionInfo &AFI = *MBB.getParent()->getInfo<AArch64FunctionInfo>();
+  bool const CanPairFillSpill = EnableSVEFillSpillPairing &&
+                                Subtarget->isSVEorStreamingSVEAvailable() &&
+                                Subtarget->getSVEVectorSizeInBits() == 128;
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paulwalker-arm wrote:

I believe the transformation should be disable for big-endian? because SVE LDR performs 8-bit accesses but SIMD LDP accesses are 128-bit.

https://github.com/llvm/llvm-project/pull/134068