[llvm] [AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bits=128. (PR #134068)

[Paul Walker via llvm-commits]

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@@ -87,6 +87,10 @@ static cl::opt<unsigned> LdStConstLimit("aarch64-load-store-const-scan-limit",
 static cl::opt<bool> EnableRenaming("aarch64-load-store-renaming",
                                     cl::init(true), cl::Hidden);
 
+// Enable SVE fill/spill pairing for VLS 128.
+static cl::opt<bool> EnableSVEFillSpillPairing("aarch64-sve-fill-spill-pairing",
+                                               cl::init(true), cl::Hidden);
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paulwalker-arm wrote:

Given the transformation is little endian specific and the option's primary use case being for debug, perhaps it's worth reversing the polarity and implementing `DisableSVEFillSpillPairing -> aarch64-disable-sve-fill-pairing`?

https://github.com/llvm/llvm-project/pull/134068