[llvm] 7cf8a62 - [AArch64,MC] Replace getSymA()->getSymbol() with getAddSym. NFC

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2025-04-05T13:51:45-07:00
New Revision: 7cf8a6201a6eb549b8d41214afa2694e0c1e344c

URL: https://github.com/llvm/llvm-project/commit/7cf8a6201a6eb549b8d41214afa2694e0c1e344c
DIFF: https://github.com/llvm/llvm-project/commit/7cf8a6201a6eb549b8d41214afa2694e0c1e344c.diff

LOG: [AArch64,MC] Replace getSymA()->getSymbol() with getAddSym. NFC

We will replace the MCSymbolRefExpr member in MCValue with MCSymbol.
This change reduces dependence on MCSymbolRefExpr.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
    llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 8b8c5a22b829c..c3baec41cbedf 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -8220,10 +8220,10 @@ bool AArch64AsmParser::classifySymbolRef(const MCExpr *Expr,
 
   // Treat expressions with an ELFSpec (like ":abs_g1:3", or
   // ":abs_g1:x" where x is constant) as symbolic even if there is no symbol.
-  if (!Res.getSymA() && ELFSpec == AArch64MCExpr::VK_INVALID)
+  if (!Res.getAddSym() && ELFSpec == AArch64MCExpr::VK_INVALID)
     return false;
 
-  if (Res.getSymA())
+  if (Res.getAddSym())
     DarwinSpec = AArch64MCExpr::Specifier(Res.getSymSpecifier());
   Addend = Res.getConstant();
 

diff  --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
index ee230a41242f6..b03c55cafdcdf 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
@@ -116,7 +116,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
   AArch64MCExpr::Specifier SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
   bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
 
-  assert((!Target.getSymA() ||
+  assert((!Target.getAddSym() ||
           Target.getSymSpecifier() == AArch64MCExpr::None ||
           Target.getSymSpecifier() == AArch64MCExpr::VK_PLT ||
           Target.getSymSpecifier() == AArch64MCExpr::VK_GOTPCREL) &&

diff  --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
index bc967e3e8a6e8..6292203ce8401 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
@@ -34,8 +34,8 @@ namespace {
 
 class AArch64MachObjectWriter : public MCMachObjectTargetWriter {
   bool getAArch64FixupKindMachOInfo(const MCFixup &Fixup, unsigned &RelocType,
-                                  const MCSymbolRefExpr *Sym,
-                                  unsigned &Log2Size, const MCAssembler &Asm);
+                                    AArch64MCExpr::Specifier Spec,
+                                    unsigned &Log2Size, const MCAssembler &Asm);
 
 public:
   AArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, bool IsILP32)
@@ -49,7 +49,7 @@ class AArch64MachObjectWriter : public MCMachObjectTargetWriter {
 } // end anonymous namespace
 
 bool AArch64MachObjectWriter::getAArch64FixupKindMachOInfo(
-    const MCFixup &Fixup, unsigned &RelocType, const MCSymbolRefExpr *Sym,
+    const MCFixup &Fixup, unsigned &RelocType, AArch64MCExpr::Specifier Spec,
     unsigned &Log2Size, const MCAssembler &Asm) {
   RelocType = unsigned(MachO::ARM64_RELOC_UNSIGNED);
   Log2Size = ~0U;
@@ -66,12 +66,12 @@ bool AArch64MachObjectWriter::getAArch64FixupKindMachOInfo(
     return true;
   case FK_Data_4:
     Log2Size = Log2_32(4);
-    if (getSpecifier(Sym) == AArch64MCExpr::M_GOT)
+    if (Spec == AArch64MCExpr::M_GOT)
       RelocType = unsigned(MachO::ARM64_RELOC_POINTER_TO_GOT);
     return true;
   case FK_Data_8:
     Log2Size = Log2_32(8);
-    if (getSpecifier(Sym) == AArch64MCExpr::M_GOT)
+    if (Spec == AArch64MCExpr::M_GOT)
       RelocType = unsigned(MachO::ARM64_RELOC_POINTER_TO_GOT);
     return true;
   case AArch64::fixup_aarch64_add_imm12:
@@ -81,7 +81,7 @@ bool AArch64MachObjectWriter::getAArch64FixupKindMachOInfo(
   case AArch64::fixup_aarch64_ldst_imm12_scale8:
   case AArch64::fixup_aarch64_ldst_imm12_scale16:
     Log2Size = Log2_32(4);
-    switch (AArch64MCExpr::Specifier(getSpecifier(Sym))) {
+    switch (Spec) {
     default:
       return false;
     case AArch64MCExpr::M_PAGEOFF:
@@ -97,7 +97,7 @@ bool AArch64MachObjectWriter::getAArch64FixupKindMachOInfo(
   case AArch64::fixup_aarch64_pcrel_adrp_imm21:
     Log2Size = Log2_32(4);
     // This encompasses the relocation for the whole 21-bit value.
-    switch (getSpecifier(Sym)) {
+    switch (Spec) {
     default:
       Asm.getContext().reportError(Fixup.getLoc(),
                                    "ADR/ADRP relocations must be GOT relative");
@@ -191,8 +191,9 @@ void AArch64MachObjectWriter::recordRelocation(
     return;
   }
 
-  if (!getAArch64FixupKindMachOInfo(Fixup, Type, Target.getSymA(), Log2Size,
-                                    Asm)) {
+  if (!getAArch64FixupKindMachOInfo(
+          Fixup, Type, AArch64MCExpr::Specifier(Target.getSymSpecifier()),
+          Log2Size, Asm)) {
     Asm.getContext().reportError(Fixup.getLoc(), "unknown AArch64 fixup kind!");
     return;
   }