[clang] [llvm] [WIP][RISC-V] prototyping intrinsic support for Zvbc32e and Zvkgs (PR #128243)

[Nicolas Brunie via llvm-commits]

================
@@ -1075,7 +1075,9 @@ constexpr static RISCVExtBit RISCVBitPositions[] = {
     {"zimop", 1, 1},      {"zca", 1, 2},
     {"zcb", 1, 3},        {"zcd", 1, 4},
     {"zcf", 1, 5},        {"zcmop", 1, 6},
-    {"zawrs", 1, 7}};
+    {"zawrs", 1, 7},      {"zvbc32e", 1, 8},
+    {"zvkgs", 1, 9}
+  };
----------------
nibrunieAtSi5 wrote:

```suggestion
    {"zvkgs", 1, 9}};
```

https://github.com/llvm/llvm-project/pull/128243