[llvm] 6f34d03 - Remove iOS 5 check for tailcalls on ARM (#133354)

[via llvm-commits]

Author: Un1q32
Date: 2025-04-04T16:02:39-07:00
New Revision: 6f34d03b3132a8286630f8496aa7dce9605e677b

URL: https://github.com/llvm/llvm-project/commit/6f34d03b3132a8286630f8496aa7dce9605e677b
DIFF: https://github.com/llvm/llvm-project/commit/6f34d03b3132a8286630f8496aa7dce9605e677b.diff

LOG: Remove iOS 5 check for tailcalls on ARM (#133354)

Fixes #102053

The check was added in 8decdc472f308b13d7fb7fd50c3919db086c0417, and at
the time iOS 5 was the latest iOS version, before that commit tail calls
were disabled for all ARMv7 targets. Testing a build of wasm3 with the
patch on a device running iOS 3.0 shows a noticeable performance
improvement and no issues.

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMSubtarget.cpp
    llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
    llvm/test/CodeGen/ARM/ldm.ll
    llvm/test/CodeGen/ARM/zextload_demandedbits.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 893084785e6f0..759070c6f08da 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -226,9 +226,6 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
 
   SupportsTailCall = !isThumb1Only() || hasV8MBaselineOps();
 
-  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
-    SupportsTailCall = false;
-
   switch (IT) {
   case DefaultIT:
     RestrictIT = false;

diff  --git a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
index ff1e769600d38..b3b6c77f9bb8f 100644
--- a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
+++ b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
@@ -9,8 +9,8 @@ entry:
 ; CHECK: mov r7, sp
 ; CHECK: bl _foo
 ; CHECK: bl _foo
-; CHECK: bl _foo
-; CHECK: pop {r7, pc}
+; CHECK: pop
+; CHECK: b
 
   %0 = tail call ptr @foo(ptr %x) nounwind
   %1 = tail call ptr @foo(ptr %0) nounwind

diff  --git a/llvm/test/CodeGen/ARM/ldm.ll b/llvm/test/CodeGen/ARM/ldm.ll
index 2f7486020890d..2d2fc578cf106 100644
--- a/llvm/test/CodeGen/ARM/ldm.ll
+++ b/llvm/test/CodeGen/ARM/ldm.ll
@@ -5,9 +5,9 @@
 
 define i32 @t1() {
 ; CHECK-LABEL: t1:
-; CHECK: pop
+; CHECK: ldrd
 ; V4T-LABEL: t1:
-; V4T: pop
+; V4T: ldm
         %tmp = load i32, ptr @X            ; <i32> [#uses=1]
         %tmp3 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 1)           ; <i32> [#uses=1]
         %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 )                ; <i32> [#uses=1]
@@ -16,9 +16,9 @@ define i32 @t1() {
 
 define i32 @t2() {
 ; CHECK-LABEL: t2:
-; CHECK: pop
+; CHECK: ldm
 ; V4T-LABEL: t2:
-; V4T: pop
+; V4T: ldm
         %tmp = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 2)            ; <i32> [#uses=1]
         %tmp3 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 3)           ; <i32> [#uses=1]
         %tmp5 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 4)           ; <i32> [#uses=1]

diff  --git a/llvm/test/CodeGen/ARM/zextload_demandedbits.ll b/llvm/test/CodeGen/ARM/zextload_demandedbits.ll
index 8519d30b7dabf..fe6febdf6e90a 100644
--- a/llvm/test/CodeGen/ARM/zextload_demandedbits.ll
+++ b/llvm/test/CodeGen/ARM/zextload_demandedbits.ll
@@ -10,8 +10,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
 ; CHECK: quux
 ; CHECK: lsl
 ; CHECK: asr
-; CHECK: bl
-; CHECK: pop
+; CHECK: b
 define void @quux(ptr %arg) {
 bb:
   %tmp1 = getelementptr inbounds %struct.eggs, ptr %arg, i32 0, i32 1