[llvm] [AMDGPU] add s_bitset[10]_b32 optimization for shl+[or, andn2] pattern (PR #134155)

[via llvm-commits]

BaoshanPang wrote:

> Need help.
> 
> This pat is not working:
> 
> ```
> +def : GCNPat <
> +  (i32 (and (i32 SSrc_b32:$src),(not (shl 1, (i32 SSrc_b32:$bit_idx))))),
> +  (i32 (S_BITSET0_B32 SSrc_b32:$bit_idx, SSrc_b32:$src))
> +>;
> ```
> 
> I want it to be used only when src and bit_idx both are SGPR, but llvm would insert a copy from VGPR to SGPR, and at later stage llvm also convert one SGPR back to VGPR which result an error. What should I do for such situation?

I am able to find a way to do it.

https://github.com/llvm/llvm-project/pull/134155