[llvm] [MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (PR #132704)

[Min-Yih Hsu via llvm-commits]

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+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=mips64el -mcpu=i6400 --mattr=msa -timeline -iterations=1 < %s | FileCheck %s
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mshockwave wrote:

I just checked the processor definitions: please correct me if I'm wrong, but it seems like none of the in-tree MIPS processors support MSA, then why did you even assign meaningful latency/occupancy to those instructions?

https://github.com/llvm/llvm-project/pull/132704