[clang] [llvm] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants (PR #134345)

[Artem Belevich via llvm-commits]

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@@ -703,6 +703,53 @@ let hasSideEffects = false in {
   defm CVT_to_tf32_rz_satf : CVT_TO_TF32<"rz.satfinite", [hasPTX<86>, hasSM<100>]>;
   defm CVT_to_tf32_rn_relu_satf  : CVT_TO_TF32<"rn.relu.satfinite", [hasPTX<86>, hasSM<100>]>;
   defm CVT_to_tf32_rz_relu_satf  : CVT_TO_TF32<"rz.relu.satfinite", [hasPTX<86>, hasSM<100>]>;
+
+  // FP6 conversions.
+  multiclass CVT_TO_F6X2<string F6Name> {
+    def _f32 :
+      NVPTXInst<(outs Int16Regs:$dst),
+                (ins Float32Regs:$src1, Float32Regs:$src2, CvtMode:$mode),
+                !strconcat("cvt${mode:base}.satfinite${mode:relu}.",
+                F6Name, "x2.f32 \t$dst, $src1, $src2;"), []>;
+  }
+
+  defm CVT_e2m3x2 : CVT_TO_F6X2<"e2m3">;
+  defm CVT_e3m2x2 : CVT_TO_F6X2<"e3m2">;
+
+  class CVT_f16x2_fp6<string F6Name> :
+    NVPTXInst<(outs Int32Regs:$dst),
+              (ins Int16Regs:$src, CvtMode:$mode),
+              !strconcat("cvt${mode:base}${mode:relu}.f16x2.",
+              F6Name, "x2 \t$dst, $src;"), []>;
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Artem-B wrote:

This should be on the same line with strconcat, or indented to be just below the start of its argument list.


https://github.com/llvm/llvm-project/pull/134345