[llvm] bbaf087 - [RISCV] Assert on all invalid inputs to getStackAdjBase and printRegList. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-04-04T13:41:05-07:00
New Revision: bbaf0877fa61ea5cadc6ded794c3184081790c66

URL: https://github.com/llvm/llvm-project/commit/bbaf0877fa61ea5cadc6ded794c3184081790c66
DIFF: https://github.com/llvm/llvm-project/commit/bbaf0877fa61ea5cadc6ded794c3184081790c66.diff

LOG: [RISCV] Assert on all invalid inputs to getStackAdjBase and printRegList. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index 7e199af98cb03..3b3460c308d7e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -241,6 +241,8 @@ float RISCVLoadFPImm::getFPImm(unsigned Imm) {
 }
 
 void RISCVZC::printRegList(unsigned RlistEncode, raw_ostream &OS) {
+  assert(RlistEncode >= RLISTENCODE::RA &&
+         RlistEncode <= RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
   OS << "{ra";
   if (RlistEncode > RISCVZC::RA) {
     OS << ", s0";

diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index d7af9d79c4cde..506c638c83a72 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -651,8 +651,8 @@ inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
 }
 
 inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
-  assert(RlistVal != RLISTENCODE::INVALID_RLIST &&
-         "{ra, s0-s10} is not supported, s11 must be included.");
+  assert(RlistVal >= RLISTENCODE::RA && RlistVal <= RLISTENCODE::RA_S0_S11 &&
+         "Invalid Rlist");
   unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1;
   // s10 and s11 are saved together.
   if (RlistVal == RLISTENCODE::RA_S0_S11)

diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 8a384020820ff..83ecf805489c1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -225,6 +225,10 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
 void RISCVInstPrinter::printRegList(const MCInst *MI, unsigned OpNo,
                                     const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
+
+  assert(Imm >= RISCVZC::RLISTENCODE::RA &&
+         Imm <= RISCVZC::RLISTENCODE::RA_S0_S11 && "Invalid Rlist");
+
   O << "{";
   printRegName(O, RISCV::X1);
 
@@ -281,7 +285,6 @@ void RISCVInstPrinter::printStackAdj(const MCInst *MI, unsigned OpNo,
   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
   int64_t StackAdj = 0;
   auto RlistVal = MI->getOperand(0).getImm();
-  assert(RlistVal != 16 && "Incorrect rlist.");
   auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64);
   StackAdj = Imm + Base;
   assert((StackAdj >= Base && StackAdj <= Base + 48) &&