[llvm] 9069ba1 - [RISCV] Rename Spimm to StackAdj in most places. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 4 12:49:36 PDT 2025
Author: Craig Topper
Date: 2025-04-04T12:49:09-07:00
New Revision: 9069ba183d0ad56a1e7b9710d9198686bc9b888b
URL: https://github.com/llvm/llvm-project/commit/9069ba183d0ad56a1e7b9710d9198686bc9b888b
DIFF: https://github.com/llvm/llvm-project/commit/9069ba183d0ad56a1e7b9710d9198686bc9b888b.diff
LOG: [RISCV] Rename Spimm to StackAdj in most places. NFC
Spimm in the spec refers to the 2-bit encoded value. All of the code
uses the 0, 16, 32, or 48 adjustment value.
Also remove the decodeZcmpSpimm as its identical to the default
behavior for no custom DecoderMethod.
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index bc725ea939aec..6c246176a05e8 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -350,7 +350,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
FRM,
Fence,
RegList,
- Spimm,
+ StackAdj,
RegReg,
} Kind;
@@ -392,7 +392,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
unsigned Encoding;
};
- struct SpimmOp {
+ struct StackAdjOp {
unsigned Val;
};
@@ -412,7 +412,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
FRMOp FRM;
FenceOp Fence;
RegListOp RegList;
- SpimmOp Spimm;
+ StackAdjOp StackAdj;
RegRegOp RegReg;
};
@@ -451,8 +451,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
case KindTy::RegList:
RegList = o.RegList;
break;
- case KindTy::Spimm:
- Spimm = o.Spimm;
+ case KindTy::StackAdj:
+ StackAdj = o.StackAdj;
break;
case KindTy::RegReg:
RegReg = o.RegReg;
@@ -486,7 +486,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
bool isRegListS0() const {
return Kind == KindTy::RegList && RegList.Encoding != RISCVZC::RA;
}
- bool isSpimm() const { return Kind == KindTy::Spimm; }
+ bool isStackAdj() const { return Kind == KindTy::StackAdj; }
bool isGPR() const {
return Kind == KindTy::Register &&
@@ -1014,9 +1014,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
RISCVZC::printRegList(RegList.Encoding, OS);
OS << '>';
break;
- case KindTy::Spimm:
- OS << "<Spimm: ";
- OS << Spimm.Val;
+ case KindTy::StackAdj:
+ OS << "<stackadj: ";
+ OS << StackAdj.Val;
OS << '>';
break;
case KindTy::RegReg:
@@ -1116,9 +1116,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return Op;
}
- static std::unique_ptr<RISCVOperand> createSpimm(unsigned Spimm, SMLoc S) {
- auto Op = std::make_unique<RISCVOperand>(KindTy::Spimm);
- Op->Spimm.Val = Spimm;
+ static std::unique_ptr<RISCVOperand> createStackAdj(unsigned StackAdj, SMLoc S) {
+ auto Op = std::make_unique<RISCVOperand>(KindTy::StackAdj);
+ Op->StackAdj.Val = StackAdj;
Op->StartLoc = S;
return Op;
}
@@ -1194,9 +1194,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createReg(RegReg.Reg2));
}
- void addSpimmOperands(MCInst &Inst, unsigned N) const {
+ void addStackAdjOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::createImm(Spimm.Val));
+ Inst.addOperand(MCOperand::createImm(StackAdj.Val));
}
void addFRMArgOperands(MCInst &Inst, unsigned N) const {
@@ -2699,8 +2699,8 @@ ParseStatus RISCVAsmParser::parseZcmpStackAdj(OperandVector &Operands,
"be a multiple of 16 bytes in the range");
}
- unsigned Spimm = (StackAdjustment - StackAdjBase) / 16;
- Operands.push_back(RISCVOperand::createSpimm(Spimm << 4, S));
+ unsigned StackAdj = (StackAdjustment - StackAdjBase);
+ Operands.push_back(RISCVOperand::createStackAdj(StackAdj, S));
Lex();
return ParseStatus::Success;
}
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 099490173bf08..716299ab896d1 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -527,8 +527,8 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
uint64_t Address,
const MCDisassembler *Decoder);
-static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder);
+static DecodeStatus decodeZcmpStackAdj(MCInst &Inst, uint32_t Imm,
+ uint64_t Address, const void *Decoder);
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
uint64_t Address,
@@ -668,12 +668,6 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
return MCDisassembler::Success;
}
-static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
- uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::createImm(Imm));
- return MCDisassembler::Success;
-}
-
// Add implied SP operand for C.*SP compressed instructions. The SP operand
// isn't explicitly encoded in the instruction.
void RISCVDisassembler::addSPOperands(MCInst &MI) const {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index f4d18dec054c1..d7af9d79c4cde 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -352,7 +352,7 @@ enum OperandType : unsigned {
OPERAND_RVKRNUM_2_14,
OPERAND_RLIST,
OPERAND_RLIST_S0,
- OPERAND_SPIMM,
+ OPERAND_STACKADJ,
// Operand is a 3-bit rounding mode, '111' indicates FRM register.
// Represents 'frm' argument passing to floating-point operations.
OPERAND_FRMARG,
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 41051e46f1bb1..c7b2b781422d1 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -962,10 +962,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
// stack space. Align the stack size down to a multiple of 16. This is
// needed for RVE.
// FIXME: Can we increase the stack size to a multiple of 16 instead?
- uint64_t Spimm =
+ uint64_t StackAdj =
std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
- FirstFrameSetup->getOperand(1).setImm(Spimm);
- StackSize -= Spimm;
+ FirstFrameSetup->getOperand(1).setImm(StackAdj);
+ StackSize -= StackAdj;
unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize - StackSize));
@@ -1278,10 +1278,10 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
// space. Align the stack size down to a multiple of 16. This is needed for
// RVE.
// FIXME: Can we increase the stack size to a multiple of 16 instead?
- uint64_t Spimm =
+ uint64_t StackAdj =
std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
- MBBI->getOperand(1).setImm(Spimm);
- StackSize -= Spimm;
+ MBBI->getOperand(1).setImm(StackAdj);
+ StackSize -= StackAdj;
if (StackSize != 0)
deallocateStack(MF, MBB, MBBI, DL, StackSize,
@@ -1984,7 +1984,7 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
MBB.addLiveIn(Reg);
// TODO: Handle QCI Interrupt + Push/Pop
} else if (RVFI->isPushable(*MF)) {
- // Emit CM.PUSH with base SPimm & evaluate Push stack
+ // Emit CM.PUSH with base StackAdj & evaluate Push stack
unsigned PushedRegNum = RVFI->getRVPushRegs();
if (PushedRegNum > 0) {
// Use encoded number to represent registers to spill.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 355bcb775cb35..44894365b6d41 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2702,8 +2702,8 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_RLIST_S0:
Ok = Imm >= RISCVZC::RA_S0 && Imm <= RISCVZC::RA_S0_S11;
break;
- case RISCVOp::OPERAND_SPIMM:
- Ok = (Imm & 0xf) == 0;
+ case RISCVOp::OPERAND_STACKADJ:
+ Ok = Imm >= 0 && Imm <= 48 && Imm % 16 == 0;
break;
case RISCVOp::OPERAND_FRMARG:
Ok = RISCVFPRndMode::isValidRoundingMode(Imm);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index bcda5331d845f..f1734405fae63 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -46,16 +46,16 @@ def StackAdjAsmOperand : AsmOperandClass {
let Name = "StackAdj";
let ParserMethod = "parseZcmpStackAdj";
let DiagnosticType = "InvalidStackAdj";
- let PredicateMethod = "isSpimm";
- let RenderMethod = "addSpimmOperands";
+ let PredicateMethod = "isStackAdj";
+ let RenderMethod = "addStackAdjOperands";
}
def NegStackAdjAsmOperand : AsmOperandClass {
let Name = "NegStackAdj";
let ParserMethod = "parseZcmpNegStackAdj";
let DiagnosticType = "InvalidStackAdj";
- let PredicateMethod = "isSpimm";
- let RenderMethod = "addSpimmOperands";
+ let PredicateMethod = "isStackAdj";
+ let RenderMethod = "addStackAdjOperands";
}
def reglist : RISCVOp<OtherVT> {
@@ -77,8 +77,7 @@ def reglist : RISCVOp<OtherVT> {
def stackadj : RISCVOp<OtherVT> {
let ParserMatchClass = StackAdjAsmOperand;
let PrintMethod = "printStackAdj";
- let DecoderMethod = "decodeZcmpSpimm";
- let OperandType = "OPERAND_SPIMM";
+ let OperandType = "OPERAND_STACKADJ";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -90,8 +89,7 @@ def stackadj : RISCVOp<OtherVT> {
def negstackadj : RISCVOp<OtherVT> {
let ParserMatchClass = NegStackAdjAsmOperand;
let PrintMethod = "printNegStackAdj";
- let DecoderMethod = "decodeZcmpSpimm";
- let OperandType = "OPERAND_SPIMM";
+ let OperandType = "OPERAND_STACKADJ";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
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