[llvm] 70a1445 - [RISCV] Prefer RegList over Rlist in assembler. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 4 09:43:09 PDT 2025
Author: Craig Topper
Date: 2025-04-04T09:37:52-07:00
New Revision: 70a1445e401f6d7b531933ab157fba98ec84f69f
URL: https://github.com/llvm/llvm-project/commit/70a1445e401f6d7b531933ab157fba98ec84f69f
DIFF: https://github.com/llvm/llvm-project/commit/70a1445e401f6d7b531933ab157fba98ec84f69f.diff
LOG: [RISCV] Prefer RegList over Rlist in assembler. NFC
This makes it more obvious what the R means. I've kept rlist in
place that refer to the encoding.
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 2fdee13a734f6..bc725ea939aec 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -215,10 +215,10 @@ class RISCVAsmParser : public MCTargetAsmParser {
ParseStatus parseGPRPair(OperandVector &Operands, bool IsRV64Inst);
ParseStatus parseFRMArg(OperandVector &Operands);
ParseStatus parseFenceArg(OperandVector &Operands);
- ParseStatus parseReglist(OperandVector &Operands) {
+ ParseStatus parseRegList(OperandVector &Operands) {
return parseRegListCommon(Operands, /*MustIncludeS0=*/false);
}
- ParseStatus parseReglistS0(OperandVector &Operands) {
+ ParseStatus parseRegListS0(OperandVector &Operands) {
return parseRegListCommon(Operands, /*MustIncludeS0=*/true);
}
ParseStatus parseRegListCommon(OperandVector &Operands, bool MustIncludeS0);
@@ -349,7 +349,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VType,
FRM,
Fence,
- Rlist,
+ RegList,
Spimm,
RegReg,
} Kind;
@@ -388,8 +388,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
unsigned Val;
};
- struct RlistOp {
- unsigned Val;
+ struct RegListOp {
+ unsigned Encoding;
};
struct SpimmOp {
@@ -411,7 +411,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VTypeOp VType;
FRMOp FRM;
FenceOp Fence;
- RlistOp Rlist;
+ RegListOp RegList;
SpimmOp Spimm;
RegRegOp RegReg;
};
@@ -448,8 +448,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
case KindTy::Fence:
Fence = o.Fence;
break;
- case KindTy::Rlist:
- Rlist = o.Rlist;
+ case KindTy::RegList:
+ RegList = o.RegList;
break;
case KindTy::Spimm:
Spimm = o.Spimm;
@@ -482,9 +482,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
bool isMem() const override { return false; }
bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
bool isRegReg() const { return Kind == KindTy::RegReg; }
- bool isRlist() const { return Kind == KindTy::Rlist; }
- bool isRlistS0() const {
- return Kind == KindTy::Rlist && Rlist.Val != RISCVZC::RA;
+ bool isRegList() const { return Kind == KindTy::RegList; }
+ bool isRegListS0() const {
+ return Kind == KindTy::RegList && RegList.Encoding != RISCVZC::RA;
}
bool isSpimm() const { return Kind == KindTy::Spimm; }
@@ -1009,9 +1009,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
OS << getFence();
OS << '>';
break;
- case KindTy::Rlist:
- OS << "<rlist: ";
- RISCVZC::printRlist(Rlist.Val, OS);
+ case KindTy::RegList:
+ OS << "<reglist: ";
+ RISCVZC::printRegList(RegList.Encoding, OS);
OS << '>';
break;
case KindTy::Spimm:
@@ -1098,10 +1098,10 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return Op;
}
- static std::unique_ptr<RISCVOperand> createRlist(unsigned RlistEncode,
+ static std::unique_ptr<RISCVOperand> createRegList(unsigned RlistEncode,
SMLoc S) {
- auto Op = std::make_unique<RISCVOperand>(KindTy::Rlist);
- Op->Rlist.Val = RlistEncode;
+ auto Op = std::make_unique<RISCVOperand>(KindTy::RegList);
+ Op->RegList.Encoding = RlistEncode;
Op->StartLoc = S;
return Op;
}
@@ -1183,9 +1183,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createImm(Imm));
}
- void addRlistOperands(MCInst &Inst, unsigned N) const {
+ void addRegListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::createImm(Rlist.Val));
+ Inst.addOperand(MCOperand::createImm(RegList.Encoding));
}
void addRegRegOperands(MCInst &Inst, unsigned N) const {
@@ -2569,13 +2569,13 @@ ParseStatus RISCVAsmParser::parseRegReg(OperandVector &Operands) {
ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
bool MustIncludeS0) {
- // Rlist: {ra [, s0[-sN]]}
- // XRlist: {x1 [, x8[-x9][, x18[-xN]]]}
+ // RegList: {ra [, s0[-sN]]}
+ // XRegList: {x1 [, x8[-x9][, x18[-xN]]]}
// When MustIncludeS0 = true (not the default) (used for `qc.cm.pushfp`) which
// must include `fp`/`s0` in the list:
- // Rlist: {ra, s0[-sN]}
- // XRlist: {x1, x8[-x9][, x18[-xN]]}
+ // RegList: {ra, s0[-sN]}
+ // XRegList: {x1, x8[-x9][, x18[-xN]]}
if (getTok().isNot(AsmToken::LCurly))
return ParseStatus::NoMatch;
@@ -2656,13 +2656,13 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
return Error(S, "invalid register list, {ra, s0-s10} or {x1, x8-x9, "
"x18-x26} is not supported");
- auto Encode = RISCVZC::encodeRlist(RegEnd, IsRVE);
+ auto Encode = RISCVZC::encodeRegList(RegEnd, IsRVE);
assert(Encode != RISCVZC::INVALID_RLIST);
if (MustIncludeS0 && Encode == RISCVZC::RA)
return Error(S, "register list must include 's0' or 'x8'");
- Operands.push_back(RISCVOperand::createRlist(Encode, S));
+ Operands.push_back(RISCVOperand::createRegList(Encode, S));
return ParseStatus::Success;
}
@@ -2677,14 +2677,14 @@ ParseStatus RISCVAsmParser::parseZcmpStackAdj(OperandVector &Operands,
int64_t StackAdjustment = getTok().getIntVal();
- auto *RListOp = static_cast<RISCVOperand *>(Operands.back().get());
- if (!RListOp->isRlist())
+ auto *RegListOp = static_cast<RISCVOperand *>(Operands.back().get());
+ if (!RegListOp->isRegList())
return ParseStatus::NoMatch;
- unsigned RlistVal = RListOp->Rlist.Val;
+ unsigned RlistEncode = RegListOp->RegList.Encoding;
- assert(RlistVal != RISCVZC::INVALID_RLIST);
- unsigned StackAdjBase = RISCVZC::getStackAdjBase(RlistVal, isRV64());
+ assert(RlistEncode != RISCVZC::INVALID_RLIST);
+ unsigned StackAdjBase = RISCVZC::getStackAdjBase(RlistEncode, isRV64());
if (Negative != ExpectNegative || StackAdjustment % 16 != 0 ||
StackAdjustment < StackAdjBase || (StackAdjustment - StackAdjBase) > 48) {
int64_t Lower = StackAdjBase;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index d5f08ac05f82b..7e199af98cb03 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -240,14 +240,14 @@ float RISCVLoadFPImm::getFPImm(unsigned Imm) {
return bit_cast<float>(I);
}
-void RISCVZC::printRlist(unsigned SlistEncode, raw_ostream &OS) {
+void RISCVZC::printRegList(unsigned RlistEncode, raw_ostream &OS) {
OS << "{ra";
- if (SlistEncode > RISCVZC::RA) {
+ if (RlistEncode > RISCVZC::RA) {
OS << ", s0";
- if (SlistEncode == RISCVZC::RA_S0_S11)
+ if (RlistEncode == RISCVZC::RA_S0_S11)
OS << "-s11";
- else if (SlistEncode > RISCVZC::RA_S0 && SlistEncode <= RISCVZC::RA_S0_S11)
- OS << "-s" << (SlistEncode - RISCVZC::RA_S0);
+ else if (RlistEncode > RISCVZC::RA_S0 && RlistEncode <= RISCVZC::RA_S0_S11)
+ OS << "-s" << (RlistEncode - RISCVZC::RA_S0);
}
OS << "}";
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index adccd1e6c5002..f4d18dec054c1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -609,7 +609,7 @@ enum RLISTENCODE {
INVALID_RLIST,
};
-inline unsigned encodeRlist(MCRegister EndReg, bool IsRVE = false) {
+inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
switch (EndReg) {
case RISCV::X1:
@@ -641,7 +641,7 @@ inline unsigned encodeRlist(MCRegister EndReg, bool IsRVE = false) {
}
}
-inline static unsigned encodeRlistNumRegs(unsigned NumRegs) {
+inline static unsigned encodeRegListNumRegs(unsigned NumRegs) {
assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 &&
"Unexpected number of registers");
if (NumRegs == 13)
@@ -662,7 +662,7 @@ inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
return alignTo(NumRegs * RegSize, 16);
}
-void printRlist(unsigned SlistEncode, raw_ostream &OS);
+void printRegList(unsigned RlistEncode, raw_ostream &OS);
} // namespace RISCVZC
namespace RISCVVInversePseudosTable {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index cd2322cc5b26d..8a384020820ff 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -222,8 +222,8 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
// Print a Zcmp RList. If we are printing architectural register names rather
// than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
// registers. Otherwise, we print "{ra, s0-s11}".
-void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O) {
+void RISCVInstPrinter::printRegList(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNo).getImm();
O << "{";
printRegName(O, RISCV::X1);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
index 6d4928ee64ec9..7463088d1bebf 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
@@ -50,8 +50,8 @@ class RISCVInstPrinter : public MCInstPrinter {
raw_ostream &O);
void printVMaskReg(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
- void printRlist(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
+ void printRegList(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+ raw_ostream &O);
void printStackAdj(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O,
bool Negate = false);
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 7a68f2878880e..41051e46f1bb1 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -1989,7 +1989,7 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
if (PushedRegNum > 0) {
// Use encoded number to represent registers to spill.
unsigned Opcode = getPushOpcode(RVFI->getPushPopKind(*MF), hasFP(*MF));
- unsigned RegEnc = RISCVZC::encodeRlistNumRegs(PushedRegNum);
+ unsigned RegEnc = RISCVZC::encodeRegListNumRegs(PushedRegNum);
MachineInstrBuilder PushBuilder =
BuildMI(MBB, MI, DL, TII.get(Opcode))
.setMIFlag(MachineInstr::FrameSetup);
@@ -2151,7 +2151,7 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters(
unsigned PushedRegNum = RVFI->getRVPushRegs();
if (PushedRegNum > 0) {
unsigned Opcode = getPopOpcode(RVFI->getPushPopKind(*MF));
- unsigned RegEnc = RISCVZC::encodeRlistNumRegs(PushedRegNum);
+ unsigned RegEnc = RISCVZC::encodeRegListNumRegs(PushedRegNum);
MachineInstrBuilder PopBuilder =
BuildMI(MBB, MI, DL, TII.get(Opcode))
.setMIFlag(MachineInstr::FrameDestroy);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td
index bee937f91f46c..228b75e33c080 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmp.td
@@ -25,17 +25,17 @@
// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//
-def RlistS0AsmOperand : AsmOperandClass {
- let Name = "RlistS0";
- let ParserMethod = "parseReglistS0";
- let RenderMethod = "addRlistOperands";
- let DiagnosticType = "InvalidRlistS0";
+def RegListS0AsmOperand : AsmOperandClass {
+ let Name = "RegListS0";
+ let ParserMethod = "parseRegListS0";
+ let RenderMethod = "addRegListOperands";
+ let DiagnosticType = "InvalidRegListS0";
let DiagnosticString = "operand must be {ra, s0[-sN]} or {x1, x8[-x9][, x18[-xN]]}";
}
-def rlist_s0 : RISCVOp<OtherVT> {
- let ParserMatchClass = RlistS0AsmOperand;
- let PrintMethod = "printRlist";
+def reglist_s0 : RISCVOp<OtherVT> {
+ let ParserMatchClass = RegListS0AsmOperand;
+ let PrintMethod = "printRegList";
let DecoderMethod = "decodeXqccmpRlistS0";
let EncoderMethod = "getRlistS0OpValue";
let MCOperandPredicate = [{
@@ -59,7 +59,7 @@ def rlist_s0 : RISCVOp<OtherVT> {
class RVInstXqccmpCPPPFP<bits<5> funct5, string opcodestr,
DAGOperand immtype = stackadj>
- : RVInst16<(outs), (ins rlist_s0:$rlist, immtype:$stackadj),
+ : RVInst16<(outs), (ins reglist_s0:$rlist, immtype:$stackadj),
opcodestr, "$rlist, $stackadj", [], InstFormatOther> {
bits<4> rlist;
bits<16> stackadj;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index 3f90714cdbe88..bcda5331d845f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -35,10 +35,10 @@ def uimm8ge32 : RISCVOp {
let OperandType = "OPERAND_UIMM8_GE32";
}
-def RlistAsmOperand : AsmOperandClass {
- let Name = "Rlist";
- let ParserMethod = "parseReglist";
- let DiagnosticType = "InvalidRlist";
+def RegListAsmOperand : AsmOperandClass {
+ let Name = "RegList";
+ let ParserMethod = "parseRegList";
+ let DiagnosticType = "InvalidRegList";
let DiagnosticString = "operand must be {ra [, s0[-sN]]} or {x1 [, x8[-x9][, x18[-xN]]]}";
}
@@ -58,9 +58,9 @@ def NegStackAdjAsmOperand : AsmOperandClass {
let RenderMethod = "addSpimmOperands";
}
-def rlist : RISCVOp<OtherVT> {
- let ParserMatchClass = RlistAsmOperand;
- let PrintMethod = "printRlist";
+def reglist : RISCVOp<OtherVT> {
+ let ParserMatchClass = RegListAsmOperand;
+ let PrintMethod = "printRegList";
let DecoderMethod = "decodeZcmpRlist";
let EncoderMethod = "getRlistOpValue";
let MCOperandPredicate = [{
@@ -155,7 +155,7 @@ class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
class RVInstZcCPPP<bits<5> funct5, string opcodestr,
DAGOperand immtype = stackadj>
- : RVInst16<(outs), (ins rlist:$rlist, immtype:$stackadj),
+ : RVInst16<(outs), (ins reglist:$rlist, immtype:$stackadj),
opcodestr, "$rlist, $stackadj", [], InstFormatOther> {
bits<4> rlist;
bits<16> stackadj;
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