[llvm] 07161a3 - [RISCV] Return NoMatch if register list does not start with a curly brace.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-04-04T08:55:37-07:00
New Revision: 07161a3fb16f07f4001de43e17d0cd487841ef98

URL: https://github.com/llvm/llvm-project/commit/07161a3fb16f07f4001de43e17d0cd487841ef98
DIFF: https://github.com/llvm/llvm-project/commit/07161a3fb16f07f4001de43e17d0cd487841ef98.diff

LOG: [RISCV] Return NoMatch if register list does not start with a curly brace.

This way we emit the error message that explains the full syntax
for a register list.

parseZcmpStackAdj had to be modified to not assume the previous
operand had been successfully parsed as a register list.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    llvm/test/MC/RISCV/rv32xqccmp-invalid.s
    llvm/test/MC/RISCV/rv32zcmp-invalid.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index d90d1dda07081..2fdee13a734f6 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2576,10 +2576,12 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
   // must include `fp`/`s0` in the list:
   // Rlist: {ra, s0[-sN]}
   // XRlist: {x1, x8[-x9][, x18[-xN]]}
-  SMLoc S = getLoc();
 
-  if (parseToken(AsmToken::LCurly, "register list must start with '{'"))
-    return ParseStatus::Failure;
+  if (getTok().isNot(AsmToken::LCurly))
+    return ParseStatus::NoMatch;
+
+  SMLoc S = getLoc();
+  Lex();
 
   bool IsRVE = isRVE();
 
@@ -2674,7 +2676,12 @@ ParseStatus RISCVAsmParser::parseZcmpStackAdj(OperandVector &Operands,
     return ParseStatus::NoMatch;
 
   int64_t StackAdjustment = getTok().getIntVal();
-  unsigned RlistVal = static_cast<RISCVOperand *>(Operands[1].get())->Rlist.Val;
+
+  auto *RListOp = static_cast<RISCVOperand *>(Operands.back().get());
+  if (!RListOp->isRlist())
+    return ParseStatus::NoMatch;
+
+  unsigned RlistVal = RListOp->Rlist.Val;
 
   assert(RlistVal != RISCVZC::INVALID_RLIST);
   unsigned StackAdjBase = RISCVZC::getStackAdjBase(RlistVal, isRV64());

diff  --git a/llvm/test/MC/RISCV/rv32xqccmp-invalid.s b/llvm/test/MC/RISCV/rv32xqccmp-invalid.s
index 5bfc2e3498bef..ece3513120392 100644
--- a/llvm/test/MC/RISCV/rv32xqccmp-invalid.s
+++ b/llvm/test/MC/RISCV/rv32xqccmp-invalid.s
@@ -37,3 +37,8 @@ qc.cm.pop {ra, s0-s1}, -40
 # CHECK-ERROR: :[[@LINE+1]]:14: error: register list must include 's0' or 'x8'
 qc.cm.pushfp {ra}, -16
 
+# CHECK-ERROR: :[[@LINE+1]]:12: error: operand must be {ra [, s0[-sN]]} or {x1 [, x8[-x9][, x18[-xN]]]}
+qc.cm.push x1, -16
+
+# CHECK-ERROR: :[[@LINE+1]]:14: error: operand must be {ra, s0[-sN]} or {x1, x8[-x9][, x18[-xN]]}
+qc.cm.pushfp x1, -16

diff  --git a/llvm/test/MC/RISCV/rv32zcmp-invalid.s b/llvm/test/MC/RISCV/rv32zcmp-invalid.s
index c41cc35a8f8ee..b4261f865fae7 100644
--- a/llvm/test/MC/RISCV/rv32zcmp-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zcmp-invalid.s
@@ -45,3 +45,6 @@ cm.pop {ra, x8-x9, x18-x17}, -40
 
 # CHECK-ERROR: :[[@LINE+1]]:16: error: invalid register
 cm.pop {ra, x8-f8, x18-x17}, -40
+
+# CHECK-ERROR: :[[@LINE+1]]:9: error: operand must be {ra [, s0[-sN]]} or {x1 [, x8[-x9][, x18[-xN]]]}
+cm.push x1, -16