[llvm] [PowerPC] Fix instruction name for dmr insert (PR #134301)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 4 07:26:38 PDT 2025
https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/134301
>From e63d5576cba1765f65e6c4fea3dcd7fef23fc0a4 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Thu, 3 Apr 2025 16:12:16 -0400
Subject: [PATCH] [PowerPC] Fix instruction name for dmr insert
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 +-
llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td | 12 +--
llvm/lib/Target/PowerPC/PPCInstrMMA.td | 4 +-
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +-
.../test/CodeGen/PowerPC/dmf-outer-product.ll | 32 +++----
llvm/test/CodeGen/PowerPC/dmr-enable.ll | 24 +++---
.../test/CodeGen/PowerPC/mmaplus-acc-spill.ll | 8 +-
.../CodeGen/PowerPC/mmaplus-intrinsics.ll | 84 +++++++++----------
llvm/test/CodeGen/PowerPC/v1024ls.ll | 8 +-
.../PowerPC/ppc-encoding-ISAFuture.txt | 8 +-
.../PowerPC/ppc64le-encoding-ISAFuture.txt | 8 +-
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 24 +++---
12 files changed, 109 insertions(+), 109 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 7f4ddae5db463..1f75425752a78 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11814,11 +11814,11 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
}
SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
- SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTFDMR512, dl, MVT::v512i1, Loads[0],
+ SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1, Loads[0],
Loads[1]),
0);
SDValue LoSub = DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32);
- SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTFDMR512_HI, dl, MVT::v512i1,
+ SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
Loads[2], Loads[3]),
0);
SDValue HiSub = DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index d4f0e222b457c..15215f7dc5faa 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -174,15 +174,15 @@ let Predicates = [IsISAFuture] in {
let P = 1;
}
- def DMXXINSTFDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
+ def DMXXINSTDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
- "dmxxinstfdmr512 $AT, $XAp, $XBp, 0", []> {
+ "dmxxinstdmr512 $AT, $XAp, $XBp, 0", []> {
let P = 0;
}
- def DMXXINSTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
+ def DMXXINSTDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
- "dmxxinstfdmr512 $AT, $XAp, $XBp, 1", []> {
+ "dmxxinstdmr512 $AT, $XAp, $XBp, 1", []> {
let P = 1;
}
@@ -190,9 +190,9 @@ let Predicates = [IsISAFuture] in {
(ins dmrrowp:$AT, u2imm:$P),
"dmxxextfdmr256 $XBp, $AT, $P", []>;
- def DMXXINSTFDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
+ def DMXXINSTDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
(ins vsrprc:$XBp, u2imm:$P),
- "dmxxinstfdmr256 $AT, $XBp, $P", []>;
+ "dmxxinstdmr256 $AT, $XBp, $P", []>;
def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
"dmmr $AT, $AB",
diff --git a/llvm/lib/Target/PowerPC/PPCInstrMMA.td b/llvm/lib/Target/PowerPC/PPCInstrMMA.td
index d94ad125d258d..23b951871d5f4 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrMMA.td
@@ -1089,9 +1089,9 @@ let Predicates = [MMA, IsNotISAFuture] in {
let Predicates = [MMA, IsISAFuture] in {
def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
- (DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
+ (DMXXINSTDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
v16i8:$vs3, v16i8:$vs2)),
- (DMXXINSTFDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
+ (DMXXINSTDMR512 ConcatsMMA.VecsToVecPair0, ConcatsMMA.VecsToVecPair1)>;
def : Pat<(v512i1 immAllZerosV), (XXSETACCZW)>;
}
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 2177dba1e5762..e1d9db0e3daa7 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1448,7 +1448,7 @@ void PPCRegisterInfo::lowerWACCRestore(MachineBasicBlock::iterator II,
FrameIndex, IsLittleEndian ? 0 : 32);
// Kill VSRpReg0, VSRpReg1 (killedRegState::Killed)
- BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTFDMR512), DestReg)
+ BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTDMR512), DestReg)
.addReg(VSRpReg0, RegState::Kill)
.addReg(VSRpReg1, RegState::Kill);
diff --git a/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll b/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
index cba52567c900d..ec43776509b44 100644
--- a/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
+++ b/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
@@ -51,10 +51,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxv v2, 16(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
@@ -71,10 +71,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
@@ -102,10 +102,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxv v2, 16(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
@@ -122,10 +122,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
@@ -153,10 +153,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxv v2, 16(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
@@ -173,10 +173,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
@@ -242,10 +242,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxv v2, 16(r4)
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
@@ -262,10 +262,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
diff --git a/llvm/test/CodeGen/PowerPC/dmr-enable.ll b/llvm/test/CodeGen/PowerPC/dmr-enable.ll
index 91b0e94cd2716..a6c99a751e2c5 100644
--- a/llvm/test/CodeGen/PowerPC/dmr-enable.ll
+++ b/llvm/test/CodeGen/PowerPC/dmr-enable.ll
@@ -39,10 +39,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmmr dmr0, dmr0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r4)
@@ -56,10 +56,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmmr dmr0, dmr0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
@@ -80,16 +80,16 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: lxvp vsp34, 0(r4)
; CHECK-NEXT: lxvp vsp36, 32(r4)
-; CHECK-NEXT: dmxxinstfdmr512 wacc_hi1, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r4)
; CHECK-NEXT: lxvp vsp36, 96(r4)
-; CHECK-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0
; CHECK-NEXT: dmxor dmr0, dmr1
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
@@ -103,16 +103,16 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: lxvp vsp34, 96(r4)
; CHECK-BE-NEXT: lxvp vsp36, 64(r4)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi1, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r4)
; CHECK-BE-NEXT: lxvp vsp36, 0(r4)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxor dmr0, dmr1
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
diff --git a/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
index c83ad73e00eda..c2c8a42c402a2 100644
--- a/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
@@ -35,7 +35,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-NEXT: vmr v28, v2
; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill
; CHECK-NEXT: ld r30, 272(r1)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp60, vsp62, 0
; CHECK-NEXT: xvf16ger2pp wacc0, v2, v4
; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
; CHECK-NEXT: stxvp vsp36, 64(r1)
@@ -43,7 +43,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-NEXT: bl foo at notoc
; CHECK-NEXT: lxvp vsp34, 64(r1)
; CHECK-NEXT: lxvp vsp36, 32(r1)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
; CHECK-NEXT: xvf16ger2pp wacc0, v28, v30
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r30)
@@ -82,7 +82,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-BE-NEXT: vmr v28, v2
; CHECK-BE-NEXT: std r30, 240(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: ld r30, 368(r1)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp60, vsp62, 0
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v2, v4
; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 112(r1)
@@ -91,7 +91,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: lxvp vsp34, 112(r1)
; CHECK-BE-NEXT: lxvp vsp36, 144(r1)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v28, v30
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r30)
diff --git a/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll b/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
index 31631d3f92d8f..41e702c94339d 100644
--- a/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
@@ -29,7 +29,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-LABEL: ass_acc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmr v3, v2
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r3)
; CHECK-NEXT: stxv v5, 32(r3)
@@ -40,7 +40,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-BE-LABEL: ass_acc:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vmr v3, v2
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r3)
; CHECK-BE-NEXT: stxv v4, 32(r3)
@@ -54,7 +54,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-O0-NEXT: # implicit-def: $vsrp17
; CHECK-O0-NEXT: vmr v3, v4
; CHECK-O0-NEXT: vmr v2, v4
-; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
+; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0
; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-NEXT: xxlor vs0, v4, v4
; CHECK-O0-NEXT: stxv vs0, 48(r3)
@@ -72,7 +72,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-O0-BE-NEXT: # implicit-def: $vsrp17
; CHECK-O0-BE-NEXT: vmr v3, v4
; CHECK-O0-BE-NEXT: vmr v2, v4
-; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
+; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0
; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)
@@ -87,7 +87,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-AIX64-LABEL: ass_acc:
; CHECK-AIX64: # %bb.0: # %entry
; CHECK-AIX64-NEXT: vmr 3, 2
-; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 34, 34, 0
+; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 34, 34, 0
; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX64-NEXT: stxv 5, 48(3)
; CHECK-AIX64-NEXT: stxv 4, 32(3)
@@ -98,7 +98,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-AIX32-LABEL: ass_acc:
; CHECK-AIX32: # %bb.0: # %entry
; CHECK-AIX32-NEXT: vmr 3, 2
-; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 34, 34, 0
+; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 34, 34, 0
; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX32-NEXT: stxv 5, 48(3)
; CHECK-AIX32-NEXT: stxv 4, 32(3)
@@ -119,7 +119,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-NEXT: lxv v5, 32(r3)
; CHECK-NEXT: lxv v2, 16(r3)
; CHECK-NEXT: lxv v4, 48(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r7)
; CHECK-NEXT: stxv v5, 32(r7)
@@ -133,7 +133,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-BE-NEXT: lxv v5, 16(r3)
; CHECK-BE-NEXT: lxv v2, 32(r3)
; CHECK-BE-NEXT: lxv v4, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r7)
; CHECK-BE-NEXT: stxv v4, 32(r7)
@@ -153,7 +153,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-NEXT: xxlor v3, vs0, vs0
; CHECK-O0-NEXT: lxv vs0, 48(r3)
; CHECK-O0-NEXT: xxlor v2, vs0, vs0
-; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-NEXT: xxlor vs0, v4, v4
; CHECK-O0-NEXT: stxv vs0, 48(r7)
@@ -177,7 +177,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-BE-NEXT: xxlor v3, vs0, vs0
; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs0
-; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)
@@ -195,7 +195,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-AIX64-NEXT: lxv 5, 16(3)
; CHECK-AIX64-NEXT: lxv 2, 32(3)
; CHECK-AIX64-NEXT: lxv 4, 0(3)
-; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 36, 34, 0
+; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 36, 34, 0
; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX64-NEXT: stxv 5, 48(5)
; CHECK-AIX64-NEXT: stxv 4, 32(5)
@@ -209,7 +209,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-AIX32-NEXT: lxv 5, 16(3)
; CHECK-AIX32-NEXT: lxv 2, 32(3)
; CHECK-AIX32-NEXT: lxv 4, 0(3)
-; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 36, 34, 0
+; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 36, 34, 0
; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX32-NEXT: stxv 5, 48(5)
; CHECK-AIX32-NEXT: stxv 4, 32(5)
@@ -233,7 +233,7 @@ define void @ld_op_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-NEXT: lxv v1, 32(r3)
; CHECK-NEXT: lxv v4, 16(r3)
; CHECK-NEXT: lxv v0, 48(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0
; CHECK-NEXT: xvi4ger8pp wacc0, v2, v2
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r7)
@@ -248,7 +248,7 @@ define void @ld_op_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-BE-NEXT: lxv v1, 16(r3)
; CHECK-BE-NEXT: lxv v4, 32(r3)
; CHECK-BE-NEXT: lxv v0, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0
; CHECK-BE-NEXT: xvi4ger8pp wacc0, v2, v2
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r7)
@@ -269,7 +269,7 @@ define void @ld_op_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-NEXT: xxlor v5, vs0, vs0
; CHECK-O0-NEXT: lxv vs0, 48(r3)
; CHECK-O0-NEXT: xxlor v4, vs0, vs0
-; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp32, 0
+; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp32, 0
; CHECK-O0-NEXT: xvi4ger8pp wacc0, v2, v2
; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-NEXT: xxlor vs0, v4, v4
@@ -294,7 +294,7 @@ define void @ld_op_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0
; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0
-; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp32, 0
+; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp32, 0
; CHECK-O0-BE-NEXT: xvi4ger8pp wacc0, v2, v2
; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
@@ -313,7 +313,7 @@ define void @ld_op_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-AIX64-NEXT: lxv 1, 16(3)
; CHECK-AIX64-NEXT: lxv 4, 32(3)
; CHECK-AIX64-NEXT: lxv 0, 0(3)
-; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 32, 36, 0
+; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 32, 36, 0
; CHECK-AIX64-NEXT: xvi4ger8pp 0, 2, 2
; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX64-NEXT: stxv 5, 48(5)
@@ -328,7 +328,7 @@ define void @ld_op_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-AIX32-NEXT: lxv 1, 16(3)
; CHECK-AIX32-NEXT: lxv 4, 32(3)
; CHECK-AIX32-NEXT: lxv 0, 0(3)
-; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 32, 36, 0
+; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 32, 36, 0
; CHECK-AIX32-NEXT: xvi4ger8pp 0, 2, 2
; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX32-NEXT: stxv 5, 48(5)
@@ -354,7 +354,7 @@ define void @ld_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-NEXT: lxv v5, 32(r3)
; CHECK-NEXT: lxv v2, 16(r3)
; CHECK-NEXT: lxv v4, 48(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r3)
; CHECK-NEXT: stxv v5, 32(r3)
@@ -372,7 +372,7 @@ define void @ld_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-BE-NEXT: lxv v5, 16(r3)
; CHECK-BE-NEXT: lxv v2, 32(r3)
; CHECK-BE-NEXT: lxv v4, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r3)
; CHECK-BE-NEXT: stxv v4, 32(r3)
@@ -396,7 +396,7 @@ define void @ld_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-NEXT: xxlor v3, vs0, vs0
; CHECK-O0-NEXT: lxv vs0, 48(r3)
; CHECK-O0-NEXT: xxlor v2, vs0, vs0
-; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-NEXT: xxlor vs3, v4, v4
; CHECK-O0-NEXT: stxv vs3, 48(r3)
@@ -424,7 +424,7 @@ define void @ld_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-BE-NEXT: xxlor v3, vs0, vs0
; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs0
-; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0
; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-BE-NEXT: xxlor vs3, v5, v5
; CHECK-O0-BE-NEXT: stxv vs3, 48(r3)
@@ -446,7 +446,7 @@ define void @ld_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-AIX64-NEXT: lxv 5, 16(3)
; CHECK-AIX64-NEXT: lxv 2, 32(3)
; CHECK-AIX64-NEXT: lxv 4, 0(3)
-; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 36, 34, 0
+; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 36, 34, 0
; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX64-NEXT: stxv 5, 48(3)
; CHECK-AIX64-NEXT: stxv 4, 32(3)
@@ -464,7 +464,7 @@ define void @ld_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-AIX32-NEXT: lxv 5, 16(3)
; CHECK-AIX32-NEXT: lxv 2, 32(3)
; CHECK-AIX32-NEXT: lxv 4, 0(3)
-; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 36, 34, 0
+; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 36, 34, 0
; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX32-NEXT: stxv 5, 48(3)
; CHECK-AIX32-NEXT: stxv 4, 32(3)
@@ -493,7 +493,7 @@ define void @ld_op_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-NEXT: lxv v1, 32(r3)
; CHECK-NEXT: lxv v4, 16(r3)
; CHECK-NEXT: lxv v0, 48(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0
; CHECK-NEXT: xvi4ger8pp wacc0, v2, v2
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r7)
@@ -508,7 +508,7 @@ define void @ld_op_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-BE-NEXT: lxv v1, 16(r3)
; CHECK-BE-NEXT: lxv v4, 32(r3)
; CHECK-BE-NEXT: lxv v0, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0
; CHECK-BE-NEXT: xvi4ger8pp wacc0, v2, v2
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r7)
@@ -529,7 +529,7 @@ define void @ld_op_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-NEXT: xxlor v5, vs0, vs0
; CHECK-O0-NEXT: lxv vs0, 48(r3)
; CHECK-O0-NEXT: xxlor v4, vs0, vs0
-; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp32, 0
+; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp32, 0
; CHECK-O0-NEXT: xvi4ger8pp wacc0, v2, v2
; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-NEXT: xxlor vs0, v4, v4
@@ -554,7 +554,7 @@ define void @ld_op_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0
; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0
-; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp32, 0
+; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp32, 0
; CHECK-O0-BE-NEXT: xvi4ger8pp wacc0, v2, v2
; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
@@ -573,7 +573,7 @@ define void @ld_op_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-AIX64-NEXT: lxv 1, 16(3)
; CHECK-AIX64-NEXT: lxv 4, 32(3)
; CHECK-AIX64-NEXT: lxv 0, 0(3)
-; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 32, 36, 0
+; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 32, 36, 0
; CHECK-AIX64-NEXT: xvi4ger8pp 0, 2, 2
; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX64-NEXT: stxv 5, 48(5)
@@ -588,7 +588,7 @@ define void @ld_op_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-AIX32-NEXT: lxv 1, 16(3)
; CHECK-AIX32-NEXT: lxv 4, 32(3)
; CHECK-AIX32-NEXT: lxv 0, 0(3)
-; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 32, 36, 0
+; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 32, 36, 0
; CHECK-AIX32-NEXT: xvi4ger8pp 0, 2, 2
; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX32-NEXT: stxv 5, 48(5)
@@ -615,7 +615,7 @@ define void @cmplx_xxmacc(ptr %ptr1, ptr %ptr2, <16 x i8> %vc1, <16 x i8> %vc2)
; CHECK-NEXT: vmr v4, v3
; CHECK-NEXT: vmr v3, v2
; CHECK-NEXT: vmr v5, v2
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-NEXT: xvf64gerpp wacc0, vsp34, v2
; CHECK-NEXT: xvf64gerpp wacc0, vsp36, v4
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
@@ -634,7 +634,7 @@ define void @cmplx_xxmacc(ptr %ptr1, ptr %ptr2, <16 x i8> %vc1, <16 x i8> %vc2)
; CHECK-BE-NEXT: vmr v4, v3
; CHECK-BE-NEXT: vmr v3, v2
; CHECK-BE-NEXT: vmr v5, v2
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp38, vsp32, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0
; CHECK-BE-NEXT: xvf64gerpp wacc0, vsp34, v2
; CHECK-BE-NEXT: xvf64gerpp wacc0, vsp36, v4
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
@@ -662,7 +662,7 @@ define void @cmplx_xxmacc(ptr %ptr1, ptr %ptr2, <16 x i8> %vc1, <16 x i8> %vc2)
; CHECK-O0-NEXT: xxlor v7, vs0, vs0
; CHECK-O0-NEXT: lxv vs0, 48(r3)
; CHECK-O0-NEXT: xxlor v6, vs0, vs0
-; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp38, vsp40, 0
+; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp40, 0
; CHECK-O0-NEXT: xxlor vs0, v5, v5
; CHECK-O0-NEXT: xvf64gerpp wacc0, vsp32, vs0
; CHECK-O0-NEXT: xxlor vs0, v4, v4
@@ -696,7 +696,7 @@ define void @cmplx_xxmacc(ptr %ptr1, ptr %ptr2, <16 x i8> %vc1, <16 x i8> %vc2)
; CHECK-O0-BE-NEXT: xxlor v7, vs0, vs0
; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
; CHECK-O0-BE-NEXT: xxlor v6, vs0, vs0
-; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp38, vsp40, 0
+; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp40, 0
; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
; CHECK-O0-BE-NEXT: xvf64gerpp wacc0, vsp32, vs0
; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
@@ -721,7 +721,7 @@ define void @cmplx_xxmacc(ptr %ptr1, ptr %ptr2, <16 x i8> %vc1, <16 x i8> %vc2)
; CHECK-AIX64-NEXT: vmr 4, 3
; CHECK-AIX64-NEXT: vmr 3, 2
; CHECK-AIX64-NEXT: vmr 5, 2
-; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 38, 32, 0
+; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 38, 32, 0
; CHECK-AIX64-NEXT: xvf64gerpp 0, 34, 2
; CHECK-AIX64-NEXT: xvf64gerpp 0, 36, 4
; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0
@@ -740,7 +740,7 @@ define void @cmplx_xxmacc(ptr %ptr1, ptr %ptr2, <16 x i8> %vc1, <16 x i8> %vc2)
; CHECK-AIX32-NEXT: vmr 4, 3
; CHECK-AIX32-NEXT: vmr 3, 2
; CHECK-AIX32-NEXT: vmr 5, 2
-; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 38, 32, 0
+; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 38, 32, 0
; CHECK-AIX32-NEXT: xvf64gerpp 0, 34, 2
; CHECK-AIX32-NEXT: xvf64gerpp 0, 36, 4
; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0
@@ -1049,7 +1049,7 @@ define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, p
; CHECK-NEXT: lxv v1, 32(r3)
; CHECK-NEXT: lxv v4, 16(r3)
; CHECK-NEXT: lxv v0, 48(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0
; CHECK-NEXT: plxvp vsp36, 8(r4), 0
; CHECK-NEXT: pmxvf64gernn wacc0, vsp36, v2, 0, 0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
@@ -1065,7 +1065,7 @@ define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, p
; CHECK-BE-NEXT: lxv v1, 16(r3)
; CHECK-BE-NEXT: lxv v4, 32(r3)
; CHECK-BE-NEXT: lxv v0, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp32, vsp36, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0
; CHECK-BE-NEXT: plxvp vsp36, 8(r4), 0
; CHECK-BE-NEXT: pmxvf64gernn wacc0, vsp36, v2, 0, 0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
@@ -1088,7 +1088,7 @@ define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, p
; CHECK-O0-NEXT: xxlor v3, vs0, vs0
; CHECK-O0-NEXT: lxv vs0, 48(r3)
; CHECK-O0-NEXT: xxlor v2, vs0, vs0
-; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp32, 0
+; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp32, 0
; CHECK-O0-NEXT: plxvp vsp34, 8(r4), 0
; CHECK-O0-NEXT: xxlor vs0, v4, v4
; CHECK-O0-NEXT: pmxvf64gernn wacc0, vsp34, vs0, 0, 0
@@ -1116,7 +1116,7 @@ define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, p
; CHECK-O0-BE-NEXT: xxlor v3, vs0, vs0
; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs0
-; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp32, 0
+; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp32, 0
; CHECK-O0-BE-NEXT: plxvp vsp34, 8(r4), 0
; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
; CHECK-O0-BE-NEXT: pmxvf64gernn wacc0, vsp34, vs0, 0, 0
@@ -1137,7 +1137,7 @@ define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, p
; CHECK-AIX64-NEXT: lxv 1, 16(3)
; CHECK-AIX64-NEXT: lxv 4, 32(3)
; CHECK-AIX64-NEXT: lxv 0, 0(3)
-; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 32, 36, 0
+; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 32, 36, 0
; CHECK-AIX64-NEXT: plxvp 36, 8(4), 0
; CHECK-AIX64-NEXT: pmxvf64gernn 0, 36, 2, 0, 0
; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0
@@ -1153,7 +1153,7 @@ define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, p
; CHECK-AIX32-NEXT: lxv 1, 16(3)
; CHECK-AIX32-NEXT: lxv 4, 32(3)
; CHECK-AIX32-NEXT: lxv 0, 0(3)
-; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 32, 36, 0
+; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 32, 36, 0
; CHECK-AIX32-NEXT: plxvp 36, 8(4), 0
; CHECK-AIX32-NEXT: pmxvf64gernn 0, 36, 2, 0, 0
; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0
diff --git a/llvm/test/CodeGen/PowerPC/v1024ls.ll b/llvm/test/CodeGen/PowerPC/v1024ls.ll
index 5ec22cbc832ba..a454241a33f3e 100644
--- a/llvm/test/CodeGen/PowerPC/v1024ls.ll
+++ b/llvm/test/CodeGen/PowerPC/v1024ls.ll
@@ -11,10 +11,10 @@ define void @v1024ls(ptr nocapture readonly %vqp, ptr nocapture %resp) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxvp vsp34, 0(r3)
; CHECK-NEXT: lxvp vsp36, 32(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-NEXT: lxvp vsp34, 64(r3)
; CHECK-NEXT: lxvp vsp36, 96(r3)
-; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r4)
; CHECK-NEXT: stxvp vsp36, 64(r4)
@@ -27,10 +27,10 @@ define void @v1024ls(ptr nocapture readonly %vqp, ptr nocapture %resp) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1
; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
-; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index 5fa01371188cd..06fdb3bd25641 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -19,16 +19,16 @@
#CHECK: dmxxextfdmr256 8, 3, 3
0xf1 0x81 0x4f 0x90
-#CHECK: dmxxinstfdmr512 1, 2, 34, 0
+#CHECK: dmxxinstdmr512 1, 2, 34, 0
0xf0 0x82 0x17 0x52
-#CHECK: dmxxinstfdmr512 1, 2, 34, 1
+#CHECK: dmxxinstdmr512 1, 2, 34, 1
0xf0 0x83 0x17 0x52
-#CHECK: dmxxinstfdmr256 3, 8, 0
+#CHECK: dmxxinstdmr256 3, 8, 0
0xf1 0x80 0x47 0x94
-#CHECK: dmxxinstfdmr256 3, 8, 3
+#CHECK: dmxxinstdmr256 3, 8, 3
0xf1 0x81 0x4f 0x94
#CHECK: dmsetdmrz 3
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 72660f97c3757..c2e32a792d39d 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -13,16 +13,16 @@
#CHECK: dmxxextfdmr256 8, 3, 3
0x90 0x4f 0x81 0xf1
-#CHECK: dmxxinstfdmr512 1, 2, 34, 0
+#CHECK: dmxxinstdmr512 1, 2, 34, 0
0x52 0x17 0x82 0xf0
-#CHECK: dmxxinstfdmr512 1, 2, 34, 1
+#CHECK: dmxxinstdmr512 1, 2, 34, 1
0x52 0x17 0x83 0xf0
-#CHECK: dmxxinstfdmr256 3, 8, 0
+#CHECK: dmxxinstdmr256 3, 8, 0
0x94 0x47 0x80 0xf1
-#CHECK: dmxxinstfdmr256 3, 8, 3
+#CHECK: dmxxinstdmr256 3, 8, 3
0x94 0x4f 0x81 0xf1
#CHECK: dmsetdmrz 3
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index f8d3f7741e52b..bd7cfc4dfebfb 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -21,21 +21,21 @@
# CHECK-LE: dmxxextfdmr256 8, 3, 3 # encoding: [0x90,0x4f,0x81,0xf1]
dmxxextfdmr256 8, 3, 3
-# CHECK-BE: dmxxinstfdmr512 1, 2, 34, 0 # encoding: [0xf0,0x82,0x17,0x52]
-# CHECK-LE: dmxxinstfdmr512 1, 2, 34, 0 # encoding: [0x52,0x17,0x82,0xf0]
- dmxxinstfdmr512 1, 2, 34, 0
+# CHECK-BE: dmxxinstdmr512 1, 2, 34, 0 # encoding: [0xf0,0x82,0x17,0x52]
+# CHECK-LE: dmxxinstdmr512 1, 2, 34, 0 # encoding: [0x52,0x17,0x82,0xf0]
+ dmxxinstdmr512 1, 2, 34, 0
-# CHECK-BE: dmxxinstfdmr512 1, 2, 34, 1 # encoding: [0xf0,0x83,0x17,0x52]
-# CHECK-LE: dmxxinstfdmr512 1, 2, 34, 1 # encoding: [0x52,0x17,0x83,0xf0]
- dmxxinstfdmr512 1, 2, 34, 1
+# CHECK-BE: dmxxinstdmr512 1, 2, 34, 1 # encoding: [0xf0,0x83,0x17,0x52]
+# CHECK-LE: dmxxinstdmr512 1, 2, 34, 1 # encoding: [0x52,0x17,0x83,0xf0]
+ dmxxinstdmr512 1, 2, 34, 1
-# CHECK-BE: dmxxinstfdmr256 3, 8, 0 # encoding: [0xf1,0x80,0x47,0x94]
-# CHECK-LE: dmxxinstfdmr256 3, 8, 0 # encoding: [0x94,0x47,0x80,0xf1]
- dmxxinstfdmr256 3, 8, 0
+# CHECK-BE: dmxxinstdmr256 3, 8, 0 # encoding: [0xf1,0x80,0x47,0x94]
+# CHECK-LE: dmxxinstdmr256 3, 8, 0 # encoding: [0x94,0x47,0x80,0xf1]
+ dmxxinstdmr256 3, 8, 0
-# CHECK-BE: dmxxinstfdmr256 3, 8, 3 # encoding: [0xf1,0x81,0x4f,0x94]
-# CHECK-LE: dmxxinstfdmr256 3, 8, 3 # encoding: [0x94,0x4f,0x81,0xf1]
- dmxxinstfdmr256 3, 8, 3
+# CHECK-BE: dmxxinstdmr256 3, 8, 3 # encoding: [0xf1,0x81,0x4f,0x94]
+# CHECK-LE: dmxxinstdmr256 3, 8, 3 # encoding: [0x94,0x4f,0x81,0xf1]
+ dmxxinstdmr256 3, 8, 3
# CHECK-BE: dmsetdmrz 3 # encoding: [0x7d,0x82,0x01,0x62]
# CHECK-LE: dmsetdmrz 3 # encoding: [0x62,0x01,0x82,0x7d]
More information about the llvm-commits
mailing list