[llvm] [AArch64] Make use of byte FPR stores for bytes extracted from vectors (PR #134117)

[Paul Walker via llvm-commits]

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@@ -3208,6 +3208,8 @@ let Predicates = [HasSVE_or_SME] in {
   // Insert scalar into undef[0]
   def : Pat<(nxv16i8 (vector_insert (nxv16i8 (undef)), (i32 FPR32:$src), 0)),
             (INSERT_SUBREG (nxv16i8 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
+  def : Pat<(nxv16i8 (vector_insert (nxv16i8 (undef)), (i64 FPR64:$src), 0)),
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paulwalker-arm wrote:

We don't really want this because it goes against the canonical form where existing code expects inserts into vectors whose element type is `i32` or smaller to take an `i32` based scalar.

https://github.com/llvm/llvm-project/pull/134117