[llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)

[Sander de Smalen via llvm-commits]

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@@ -1585,6 +1585,26 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::MSTORE, VT, Custom);
     }
 
+    if (EnablePartialReduceNodes) {
+      for (MVT VT : MVT::integer_scalable_vector_valuetypes()) {
+        for (MVT InnerVT : MVT::integer_scalable_vector_valuetypes()) {
+          // 1. Set all combinations where a type is illegal to "Legal"
+          // - These will be legalized to a legal type pair
+          // - Avoid expanding them too early (or preventing folds)
+          if (!isTypeLegal(VT) || !isTypeLegal(InnerVT)) {
+            setPartialReduceMLAAction(VT, InnerVT, Legal);
+            continue;
+          }
+          //  2. Set all legal combinations to "Expand"
+          // - Not all of these can be lowered (via a Legal or Custom lowering).
+          setPartialReduceMLAAction(VT, InnerVT, Expand);
+        }
+      }
+      // 3. Mark known legal pairs as 'Legal' (these will expand to USDOT).
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sdesmalen-arm wrote:

Yes, we'll need to do custom lowering for USDOT because it's probably a bit too target-specific to warrant creating a generic ISD node for it. That said, I think there is value in encoding the extensions as well so that it can be used by the cost-model/TTI (see `TargetTransformInfo::getPartialReductionCost`, which takes a `PartialReductionExtendKind` for both operands) to figure out whether or not such an operation is legal/custom for the given types and given extensions. But that doesn't necessarily need doing in this PR.

https://github.com/llvm/llvm-project/pull/130933