[llvm] ebacd46 - [SPARC][MC] Add tests for VIS family instructions
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 3 05:55:21 PDT 2025
Author: Koakuma
Date: 2025-04-03T19:55:18+07:00
New Revision: ebacd46996a7f041be73cf31b5776503e8061e8b
URL: https://github.com/llvm/llvm-project/commit/ebacd46996a7f041be73cf31b5776503e8061e8b
DIFF: https://github.com/llvm/llvm-project/commit/ebacd46996a7f041be73cf31b5776503e8061e8b.diff
LOG: [SPARC][MC] Add tests for VIS family instructions
Also fix up any mistakes/typos in instruction definitions.
Reviewers: rorth, s-barannikov, brad0, MaskRay
Reviewed By: s-barannikov
Pull Request: https://github.com/llvm/llvm-project/pull/130967
Added:
llvm/test/MC/Disassembler/Sparc/sparc-vis.txt
llvm/test/MC/Sparc/sparc-vis2.s
llvm/test/MC/Sparc/sparc-vis3.s
Modified:
llvm/lib/Target/Sparc/SparcInstrFormats.td
llvm/lib/Target/Sparc/SparcInstrInfo.td
llvm/lib/Target/Sparc/SparcInstrVIS.td
llvm/test/MC/Sparc/sparc-vis.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 3939f4ed94276..4ff902b190a3b 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -201,6 +201,21 @@ class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
let Inst{4-0} = rs2;
}
+// SIAM instruction
+class F3_3_siam<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
+ string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
+ : F3<outs, ins, asmstr, pattern, itin> {
+ bits<3> mode;
+
+ let op = opVal;
+ let op3 = op3val;
+ let rd = 0;
+ let rs1 = 0;
+ let Inst{13-5} = opfval; // fp opcode
+ let Inst{4-3} = 0;
+ let Inst{2-0} = mode;
+}
+
// Shift by register rs2.
class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index c3b1fdf14d73e..d5af2000d0481 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -82,6 +82,9 @@ def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
// Instruction Pattern Stuff
//===----------------------------------------------------------------------===//
+// FIXME these should have AsmOperandClass.
+def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;
+
def simm10 : PatLeaf<(imm), [{ return isInt<10>(N->getSExtValue()); }]>;
def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index bdefc70869d74..8ce8f37f34040 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -7,76 +7,91 @@
//===----------------------------------------------------------------------===//
//
// This file contains instruction formats, definitions and patterns needed for
-// VIS, VIS II, VIS II instructions on SPARC.
+// VIS, VIS II, VIS III instructions on SPARC.
//===----------------------------------------------------------------------===//
// VIS Instruction Format.
-class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
- list<dag> pattern>
- : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
+class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr>
+ : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, []>;
class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
: VISInstFormat<opfval,
(outs RC:$rd), (ins RC:$rs1, RC:$rs2),
- !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
+ !strconcat(OpcStr, " $rs1, $rs2, $rd")>;
// VIS Instruction with integer destination register.
class VISInstID<bits<9> opfval, string OpcStr>
: VISInstFormat<opfval,
(outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
- !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
+ !strconcat(OpcStr, " $rs1, $rs2, $rd")>;
// For VIS Instructions with no operand.
let rd = 0, rs1 = 0, rs2 = 0 in
class VISInst0<bits<9> opfval, string asmstr>
- : VISInstFormat<opfval, (outs), (ins), asmstr, []>;
+ : VISInstFormat<opfval, (outs), (ins), asmstr>;
// For VIS Instructions with only rs1, rd operands.
let rs2 = 0 in
class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
: VISInstFormat<opfval,
(outs RC:$rd), (ins RC:$rs1),
- !strconcat(OpcStr, " $rs1, $rd"), []>;
+ !strconcat(OpcStr, " $rs1, $rd")>;
// For VIS Instructions with only rs2, rd operands.
let rs1 = 0 in
class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
: VISInstFormat<opfval,
(outs RC:$rd), (ins RC:$rs2),
- !strconcat(OpcStr, " $rs2, $rd"), []>;
+ !strconcat(OpcStr, " $rs2, $rd")>;
// For VIS Instructions with only rd operand.
let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
: VISInstFormat<opfval,
(outs RC:$rd), (ins RC:$f),
- !strconcat(OpcStr, " $rd"), []>;
+ !strconcat(OpcStr, " $rd")>;
// VIS 1 Instructions
let Predicates = [HasVIS] in {
def FPADD16 : VISInst<0b001010000, "fpadd16">;
-def FPADD16S : VISInst<0b001010001, "fpadd16s">;
+def FPADD16S : VISInst<0b001010001, "fpadd16s", FPRegs>;
def FPADD32 : VISInst<0b001010010, "fpadd32">;
-def FPADD32S : VISInst<0b001010011, "fpadd32s">;
+def FPADD32S : VISInst<0b001010011, "fpadd32s", FPRegs>;
def FPSUB16 : VISInst<0b001010100, "fpsub16">;
-def FPSUB16S : VISInst<0b001010101, "fpsub16S">;
+def FPSUB16S : VISInst<0b001010101, "fpsub16s", FPRegs>;
def FPSUB32 : VISInst<0b001010110, "fpsub32">;
-def FPSUB32S : VISInst<0b001010111, "fpsub32S">;
+def FPSUB32S : VISInst<0b001010111, "fpsub32s", FPRegs>;
def FPACK16 : VISInst2<0b000111011, "fpack16">;
def FPACK32 : VISInst <0b000111010, "fpack32">;
-def FPACKFIX : VISInst2<0b000111101, "fpackfix">;
-def FEXPAND : VISInst2<0b001001101, "fexpand">;
-def FPMERGE : VISInst <0b001001011, "fpmerge">;
-
-def FMUL8X16 : VISInst<0b000110001, "fmul8x16">;
-def FMUL8X16AU : VISInst<0b000110011, "fmul8x16au">;
-def FMUL8X16AL : VISInst<0b000110101, "fmul8x16al">;
+let rs1 = 0 in
+def FPACKFIX : VISInstFormat<0b000111101,
+ (outs FPRegs:$rd), (ins DFPRegs:$rs2), "fpackfix $rs2, $rd">;
+let rs1 = 0 in
+def FEXPAND : VISInstFormat<0b001001101,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs2), "fexpand $rs2, $rd">;
+def FPMERGE : VISInstFormat<0b001001011,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fpmerge $rs1, $rs2, $rd">;
+
+def FMUL8X16 : VISInstFormat<0b000110001,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, DFPRegs:$rs2),
+ "fmul8x16 $rs1, $rs2, $rd">;
+def FMUL8X16AU : VISInstFormat<0b000110011,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fmul8x16au $rs1, $rs2, $rd">;
+def FMUL8X16AL : VISInstFormat<0b000110101,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fmul8x16al $rs1, $rs2, $rd">;
def FMUL8SUX16 : VISInst<0b000110110, "fmul8sux16">;
def FMUL8ULX16 : VISInst<0b000110111, "fmul8ulx16">;
-def FMULD8SUX16 : VISInst<0b000111000, "fmuld8sux16">;
-def FMULD8ULX16 : VISInst<0b000111001, "fmuld8ulx16">;
+def FMULD8SUX16 : VISInstFormat<0b000111000,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fmuld8sux16 $rs1, $rs2, $rd">;
+def FMULD8ULX16 : VISInstFormat<0b000111001,
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fmuld8ulx16 $rs1, $rs2, $rd">;
def ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>;
def ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>;
@@ -148,9 +163,11 @@ def SHUTDOWN : VISInst0<0b010000000, "shutdown">;
let Predicates = [HasVIS2] in {
def BMASK : VISInst<0b000011001, "bmask", I64Regs>;
-def BSHUFFLE : VISInst<0b000011100, "bshuffle">;
+def BSHUFFLE : VISInst<0b001001100, "bshuffle">;
-def SIAM : VISInst0<0b010000001, "siam">;
+let rd = 0, rs1 = 0 in
+def SIAM : F3_3_siam<0b10, 0b110110, 0b010000001, (outs),
+ (ins i32imm:$mode), "siam $mode", []>;
def EDGE8N : VISInst<0b000000001, "edge8n", I64Regs>;
def EDGE8LN : VISInst<0b000000011, "edge8ln", I64Regs>;
@@ -172,59 +189,59 @@ def ADDXCCC : VISInst<0b000010011, "addxccc", I64Regs>;
let rd = 0, rs1 = 0 in {
def CMASK8 : VISInstFormat<0b000011011, (outs), (ins I64Regs:$rs2),
- "cmask8 $rs2", []>;
+ "cmask8 $rs2">;
def CMASK16 : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2),
- "cmask16 $rs2", []>;
+ "cmask16 $rs2">;
def CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
- "cmask32 $rs2", []>;
+ "cmask32 $rs2">;
}
def FCHKSM16 : VISInst<0b001000100, "fchksm16">;
def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fhadds $rs1, $rs2, $rd", []>;
def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fhaddd $rs1, $rs2, $rd", []>;
def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fhsubs $rs1, $rs2, $rd", []>;
def FHSUBD : F3_3<0b10, 0b110100, 0b001100110,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fhsubd $rs1, $rs2, $rd", []>;
def FLCMPS : VISInstFormat<0b101010001, (outs FCCRegs:$rd),
- (ins DFPRegs:$rs1, DFPRegs:$rs2),
- "flcmps $rd, $rs1, $rs2", []>;
+ (ins FPRegs:$rs1, FPRegs:$rs2),
+ "flcmps $rd, $rs1, $rs2">;
def FLCMPD : VISInstFormat<0b101010010, (outs FCCRegs:$rd),
(ins DFPRegs:$rs1, DFPRegs:$rs2),
- "flcmpd $rd, $rs1, $rs2", []>;
+ "flcmpd $rd, $rs1, $rs2">;
def FMEAN16 : VISInst<0b001000000, "fmean16">;
def FNADDS : F3_3<0b10, 0b110100, 0b001010001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fnadds $rs1, $rs2, $rd", []>;
def FNADDD : F3_3<0b10, 0b110100, 0b001010010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fnaddd $rs1, $rs2, $rd", []>;
def FNHADDS : F3_3<0b10, 0b110100, 0b001110001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fnhadds $rs1, $rs2, $rd", []>;
def FNHADDD : F3_3<0b10, 0b110100, 0b001110010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fnhaddd $rs1, $rs2, $rd", []>;
def FNMULS : F3_3<0b10, 0b110100, 0b001011001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
- "fnhadds $rs1, $rs2, $rd", []>;
+ (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fnmuls $rs1, $rs2, $rd", []>;
def FNMULD : F3_3<0b10, 0b110100, 0b001011010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
- "fnhaddd $rs1, $rs2, $rd", []>;
+ "fnmuld $rs1, $rs2, $rd", []>;
def FNSMULD : F3_3<0b10, 0b110100, 0b001111001,
- (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
- "fnhadds $rs1, $rs2, $rd", []>;
+ (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
+ "fnsmuld $rs1, $rs2, $rd", []>;
def FPADD64 : VISInst<0b001000010, "fpadd64">;
@@ -239,24 +256,24 @@ def FSRA32 : VISInst<0b000101111, "fsra32">;
let rs1 = 0 in
def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
- (ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
+ (ins I64Regs:$rs2), "lzcnt $rs2, $rd">;
let rs1 = 0 in {
def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
- (ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;
+ (ins DFPRegs:$rs2), "movstosw $rs2, $rd">;
def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd),
- (ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>;
+ (ins DFPRegs:$rs2), "movstouw $rs2, $rd">;
def MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd),
- (ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>;
+ (ins DFPRegs:$rs2), "movdtox $rs2, $rd">;
def MOVWTOS : VISInstFormat<0b100011001, (outs DFPRegs:$rd),
- (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
+ (ins I64Regs:$rs2), "movwtos $rs2, $rd">;
def MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd),
- (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
+ (ins I64Regs:$rs2), "movxtod $rs2, $rd">;
}
-def PDISTN : VISInst<0b000111111, "pdistn">;
+def PDISTN : VISInstID<0b000111111, "pdistn">;
def UMULXHI : VISInst<0b000010110, "umulxhi", I64Regs>;
def XMULX : VISInst<0b100010101, "xmulx", I64Regs>;
-def XMULXHI : VISInst<0b100010111, "xmulxhi", I64Regs>;
+def XMULXHI : VISInst<0b100010110, "xmulxhi", I64Regs>;
} // Predicates = [IsVIS3]
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-vis.txt b/llvm/test/MC/Disassembler/Sparc/sparc-vis.txt
new file mode 100644
index 0000000000000..56105fb41e8a5
--- /dev/null
+++ b/llvm/test/MC/Disassembler/Sparc/sparc-vis.txt
@@ -0,0 +1,291 @@
+# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+vis,+vis2,+vis3 | FileCheck %s
+
+## VIS 1 instructions.
+
+# CHECK: fpadd16 %f0, %f2, %f4
+0x89,0xb0,0x0a,0x02
+# CHECK: fpadd16s %f1, %f3, %f5
+0x8b,0xb0,0x4a,0x23
+# CHECK: fpadd32 %f0, %f2, %f4
+0x89,0xb0,0x0a,0x42
+# CHECK: fpadd32s %f1, %f3, %f5
+0x8b,0xb0,0x4a,0x63
+# CHECK: fpsub16 %f0, %f2, %f4
+0x89,0xb0,0x0a,0x82
+# CHECK: fpsub16s %f1, %f3, %f5
+0x8b,0xb0,0x4a,0xa3
+# CHECK: fpsub32 %f0, %f2, %f4
+0x89,0xb0,0x0a,0xc2
+# CHECK: fpsub32s %f1, %f3, %f5
+0x8b,0xb0,0x4a,0xe3
+
+# CHECK: fpack16 %f0, %f2
+0x85,0xb0,0x07,0x60
+# CHECK: fpack32 %f0, %f2, %f4
+0x89,0xb0,0x07,0x42
+# CHECK: fpackfix %f0, %f3
+0x87,0xb0,0x07,0xa0
+# CHECK: fexpand %f1, %f2
+0x85,0xb0,0x09,0xa1
+# CHECK: fpmerge %f1, %f3, %f4
+0x89,0xb0,0x49,0x63
+
+# CHECK: fmul8x16 %f1, %f2, %f4
+0x89,0xb0,0x46,0x22
+# CHECK: fmul8x16au %f1, %f3, %f4
+0x89,0xb0,0x46,0x63
+# CHECK: fmul8x16al %f1, %f3, %f4
+0x89,0xb0,0x46,0xa3
+# CHECK: fmul8sux16 %f0, %f2, %f4
+0x89,0xb0,0x06,0xc2
+# CHECK: fmul8ulx16 %f0, %f2, %f4
+0x89,0xb0,0x06,0xe2
+# CHECK: fmuld8sux16 %f1, %f3, %f4
+0x89,0xb0,0x47,0x03
+# CHECK: fmuld8ulx16 %f1, %f3, %f4
+0x89,0xb0,0x47,0x23
+
+# CHECK: alignaddr %o0, %o1, %o2
+0x95,0xb2,0x03,0x09
+# CHECK: alignaddrl %o0, %o1, %o2
+0x95,0xb2,0x03,0x49
+# CHECK: faligndata %f0, %f2, %f4
+0x89,0xb0,0x09,0x02
+
+# CHECK: fzero %f0
+0x81,0xb0,0x0c,0x00
+# CHECK: fzeros %f1
+0x83,0xb0,0x0c,0x20
+# CHECK: fone %f0
+0x81,0xb0,0x0f,0xc0
+# CHECK: fones %f1
+0x83,0xb0,0x0f,0xe0
+# CHECK: fsrc1 %f0, %f2
+0x85,0xb0,0x0e,0x80
+# CHECK: fsrc1s %f1, %f3
+0x87,0xb0,0x4e,0xa0
+# CHECK: fsrc2 %f0, %f2
+0x85,0xb0,0x0f,0x00
+# CHECK: fsrc2s %f1, %f3
+0x87,0xb0,0x0f,0x21
+# CHECK: fnot1 %f0, %f2
+0x85,0xb0,0x0d,0x40
+# CHECK: fnot1s %f1, %f3
+0x87,0xb0,0x4d,0x60
+# CHECK: fnot2 %f0, %f2
+0x85,0xb0,0x0c,0xc0
+# CHECK: fnot2s %f1, %f3
+0x87,0xb0,0x0c,0xe1
+# CHECK: for %f0, %f2, %f4
+0x89,0xb0,0x0f,0x82
+# CHECK: fors %f1, %f3, %f5
+0x8b,0xb0,0x4f,0xa3
+# CHECK: fnor %f0, %f2, %f4
+0x89,0xb0,0x0c,0x42
+# CHECK: fnors %f1, %f3, %f5
+0x8b,0xb0,0x4c,0x63
+# CHECK: fand %f0, %f2, %f4
+0x89,0xb0,0x0e,0x02
+# CHECK: fands %f1, %f3, %f5
+0x8b,0xb0,0x4e,0x23
+# CHECK: fnand %f0, %f2, %f4
+0x89,0xb0,0x0d,0xc2
+# CHECK: fnands %f1, %f3, %f5
+0x8b,0xb0,0x4d,0xe3
+# CHECK: fxor %f0, %f2, %f4
+0x89,0xb0,0x0d,0x82
+# CHECK: fxors %f1, %f3, %f5
+0x8b,0xb0,0x4d,0xa3
+# CHECK: fxnor %f0, %f2, %f4
+0x89,0xb0,0x0e,0x42
+# CHECK: fxnors %f1, %f3, %f5
+0x8b,0xb0,0x4e,0x63
+
+# CHECK: fornot1 %f0, %f2, %f4
+0x89,0xb0,0x0f,0x42
+# CHECK: fornot1s %f1, %f3, %f5
+0x8b,0xb0,0x4f,0x63
+# CHECK: fornot2 %f0, %f2, %f4
+0x89,0xb0,0x0e,0xc2
+# CHECK: fornot2s %f1, %f3, %f5
+0x8b,0xb0,0x4e,0xe3
+# CHECK: fandnot1 %f0, %f2, %f4
+0x89,0xb0,0x0d,0x02
+# CHECK: fandnot1s %f1, %f3, %f5
+0x8b,0xb0,0x4d,0x23
+# CHECK: fandnot2 %f0, %f2, %f4
+0x89,0xb0,0x0c,0x82
+# CHECK: fandnot2s %f1, %f3, %f5
+0x8b,0xb0,0x4c,0xa3
+
+# CHECK: fcmpgt16 %f0, %f2, %o0
+0x91,0xb0,0x05,0x02
+# CHECK: fcmpgt32 %f0, %f2, %o0
+0x91,0xb0,0x05,0x82
+# CHECK: fcmple16 %f0, %f2, %o0
+0x91,0xb0,0x04,0x02
+# CHECK: fcmple32 %f0, %f2, %o0
+0x91,0xb0,0x04,0x82
+# CHECK: fcmpne16 %f0, %f2, %o0
+0x91,0xb0,0x04,0x42
+# CHECK: fcmpne32 %f0, %f2, %o0
+0x91,0xb0,0x04,0xc2
+# CHECK: fcmpeq16 %f0, %f2, %o0
+0x91,0xb0,0x05,0x42
+# CHECK: fcmpeq32 %f0, %f2, %o0
+0x91,0xb0,0x05,0xc2
+
+# CHECK: edge8 %o0, %o1, %o2
+0x95,0xb2,0x00,0x09
+# CHECK: edge8l %o0, %o1, %o2
+0x95,0xb2,0x00,0x49
+# CHECK: edge16 %o0, %o1, %o2
+0x95,0xb2,0x00,0x89
+# CHECK: edge16l %o0, %o1, %o2
+0x95,0xb2,0x00,0xc9
+# CHECK: edge32 %o0, %o1, %o2
+0x95,0xb2,0x01,0x09
+# CHECK: edge32l %o0, %o1, %o2
+0x95,0xb2,0x01,0x49
+
+# CHECK: pdist %f0, %f2, %f4
+0x89,0xb0,0x07,0xc2
+
+# CHECK: array8 %o0, %o1, %o2
+0x95,0xb2,0x02,0x09
+# CHECK: array16 %o0, %o1, %o2
+0x95,0xb2,0x02,0x49
+# CHECK: array32 %o0, %o1, %o2
+0x95,0xb2,0x02,0x89
+
+# CHECK: shutdown
+0x81,0xb0,0x10,0x00
+
+## VIS 2 instructions.
+
+# CHECK: bmask %o0, %o1, %o2
+0x95,0xb2,0x03,0x29
+# CHECK: bshuffle %f0, %f2, %f4
+0x89,0xb0,0x09,0x82
+
+# CHECK: siam 0
+0x81,0xb0,0x10,0x20
+# CHECK: siam 1
+0x81,0xb0,0x10,0x21
+# CHECK: siam 2
+0x81,0xb0,0x10,0x22
+# CHECK: siam 3
+0x81,0xb0,0x10,0x23
+# CHECK: siam 4
+0x81,0xb0,0x10,0x24
+# CHECK: siam 5
+0x81,0xb0,0x10,0x25
+# CHECK: siam 6
+0x81,0xb0,0x10,0x26
+# CHECK: siam 7
+0x81,0xb0,0x10,0x27
+
+# CHECK: edge8n %o0, %o1, %o2
+0x95,0xb2,0x00,0x29
+# CHECK: edge8ln %o0, %o1, %o2
+0x95,0xb2,0x00,0x69
+# CHECK: edge16n %o0, %o1, %o2
+0x95,0xb2,0x00,0xa9
+# CHECK: edge16ln %o0, %o1, %o2
+0x95,0xb2,0x00,0xe9
+# CHECK: edge32n %o0, %o1, %o2
+0x95,0xb2,0x01,0x29
+# CHECK: edge32ln %o0, %o1, %o2
+0x95,0xb2,0x01,0x69
+
+## VIS 3 instructions.
+
+# CHECK: addxc %o0, %o1, %o2
+0x95,0xb2,0x02,0x29
+# CHECK: addxccc %o0, %o1, %o2
+0x95,0xb2,0x02,0x69
+
+# CHECK: cmask8 %o0
+0x81,0xb0,0x03,0x68
+# CHECK: cmask16 %o0
+0x81,0xb0,0x03,0xa8
+# CHECK: cmask32 %o0
+0x81,0xb0,0x03,0xe8
+
+# CHECK: fchksm16 %f0, %f2, %f4
+0x89,0xb0,0x08,0x82
+# CHECK: fmean16 %f0, %f2, %f4
+0x89,0xb0,0x08,0x02
+
+# CHECK: fhadds %f1, %f3, %f5
+0x8b,0xa0,0x4c,0x23
+# CHECK: fhaddd %f0, %f2, %f4
+0x89,0xa0,0x0c,0x42
+# CHECK: fhsubs %f1, %f3, %f5
+0x8b,0xa0,0x4c,0xa3
+# CHECK: fhsubd %f0, %f2, %f4
+0x89,0xa0,0x0c,0xc2
+# CHECK: flcmps %fcc0, %f3, %f5
+0x81,0xb0,0xea,0x25
+# CHECK: flcmpd %fcc0, %f2, %f4
+0x81,0xb0,0xaa,0x44
+
+# CHECK: fnadds %f1, %f3, %f5
+0x8b,0xa0,0x4a,0x23
+# CHECK: fnaddd %f0, %f2, %f4
+0x89,0xa0,0x0a,0x42
+# CHECK: fnhadds %f1, %f3, %f5
+0x8b,0xa0,0x4e,0x23
+# CHECK: fnhaddd %f0, %f2, %f4
+0x89,0xa0,0x0e,0x42
+
+# CHECK: fnmuls %f1, %f3, %f5
+0x8b,0xa0,0x4b,0x23
+# CHECK: fnmuld %f0, %f2, %f4
+0x89,0xa0,0x0b,0x42
+# CHECK: fnsmuld %f1, %f3, %f4
+0x89,0xa0,0x4f,0x23
+
+# CHECK: fpadd64 %f0, %f2, %f4
+0x89,0xb0,0x08,0x42
+
+# CHECK: fsll16 %f0, %f2, %f4
+0x89,0xb0,0x04,0x22
+# CHECK: fsrl16 %f0, %f2, %f4
+0x89,0xb0,0x04,0x62
+# CHECK: fsll32 %f0, %f2, %f4
+0x89,0xb0,0x04,0xa2
+# CHECK: fsrl32 %f0, %f2, %f4
+0x89,0xb0,0x04,0xe2
+# CHECK: fslas16 %f0, %f2, %f4
+0x89,0xb0,0x05,0x22
+# CHECK: fsra16 %f0, %f2, %f4
+0x89,0xb0,0x05,0x62
+# CHECK: fslas32 %f0, %f2, %f4
+0x89,0xb0,0x05,0xa2
+# CHECK: fsra32 %f0, %f2, %f4
+0x89,0xb0,0x05,0xe2
+
+# CHECK: lzcnt %o0, %o1
+0x93,0xb0,0x02,0xe8
+
+# CHECK: movstosw %f0, %o0
+0x91,0xb0,0x22,0x60
+# CHECK: movstouw %f0, %o0
+0x91,0xb0,0x22,0x20
+# CHECK: movdtox %f0, %o0
+0x91,0xb0,0x22,0x00
+# CHECK: movwtos %o0, %f0
+0x81,0xb0,0x23,0x28
+# CHECK: movxtod %o0, %f0
+0x81,0xb0,0x23,0x08
+
+# CHECK: pdistn %f0, %f2, %o0
+0x91,0xb0,0x07,0xe2
+
+# CHECK: umulxhi %o0, %o1, %o2
+0x95,0xb2,0x02,0xc9
+# CHECK: xmulx %o0, %o1, %o2
+0x95,0xb2,0x22,0xa9
+# CHECK: xmulxhi %o0, %o1, %o2
+0x95,0xb2,0x22,0xc9
diff --git a/llvm/test/MC/Sparc/sparc-vis.s b/llvm/test/MC/Sparc/sparc-vis.s
index 77e1ab1432eed..771d036e32db5 100644
--- a/llvm/test/MC/Sparc/sparc-vis.s
+++ b/llvm/test/MC/Sparc/sparc-vis.s
@@ -1,4 +1,237 @@
-! RUN: llvm-mc %s -triple=sparcv9 -mcpu=niagara -show-encoding | FileCheck %s
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS --implicit-check-not=error:
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis -show-encoding | FileCheck %s --check-prefixes=VIS
- ! CHECK: fzeros %f31 ! encoding: [0xbf,0xb0,0x0c,0x20]
- fzeros %f31
+!! VIS 1 instructions.
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpadd16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0a,0x02]
+fpadd16 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpadd16s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4a,0x23]
+fpadd16s %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpadd32 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0a,0x42]
+fpadd32 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpadd32s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4a,0x63]
+fpadd32s %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpsub16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0a,0x82]
+fpsub16 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpsub16s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4a,0xa3]
+fpsub16s %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpsub32 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0a,0xc2]
+fpsub32 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpsub32s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4a,0xe3]
+fpsub32s %f1, %f3, %f5
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpack16 %f0, %f2 ! encoding: [0x85,0xb0,0x07,0x60]
+fpack16 %f0, %f2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpack32 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x07,0x42]
+fpack32 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpackfix %f0, %f3 ! encoding: [0x87,0xb0,0x07,0xa0]
+fpackfix %f0, %f3
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fexpand %f1, %f2 ! encoding: [0x85,0xb0,0x09,0xa1]
+fexpand %f1, %f2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fpmerge %f1, %f3, %f4 ! encoding: [0x89,0xb0,0x49,0x63]
+fpmerge %f1, %f3, %f4
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fmul8x16 %f1, %f2, %f4 ! encoding: [0x89,0xb0,0x46,0x22]
+fmul8x16 %f1, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fmul8x16au %f1, %f3, %f4 ! encoding: [0x89,0xb0,0x46,0x63]
+fmul8x16au %f1, %f3, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fmul8x16al %f1, %f3, %f4 ! encoding: [0x89,0xb0,0x46,0xa3]
+fmul8x16al %f1, %f3, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fmul8sux16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x06,0xc2]
+fmul8sux16 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fmul8ulx16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x06,0xe2]
+fmul8ulx16 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fmuld8sux16 %f1, %f3, %f4 ! encoding: [0x89,0xb0,0x47,0x03]
+fmuld8sux16 %f1, %f3, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fmuld8ulx16 %f1, %f3, %f4 ! encoding: [0x89,0xb0,0x47,0x23]
+fmuld8ulx16 %f1, %f3, %f4
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: alignaddr %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x03,0x09]
+alignaddr %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: alignaddrl %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x03,0x49]
+alignaddrl %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: faligndata %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x09,0x02]
+faligndata %f0, %f2, %f4
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fzero %f0 ! encoding: [0x81,0xb0,0x0c,0x00]
+fzero %f0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fzeros %f1 ! encoding: [0x83,0xb0,0x0c,0x20]
+fzeros %f1
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fone %f0 ! encoding: [0x81,0xb0,0x0f,0xc0]
+fone %f0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fones %f1 ! encoding: [0x83,0xb0,0x0f,0xe0]
+fones %f1
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fsrc1 %f0, %f2 ! encoding: [0x85,0xb0,0x0e,0x80]
+fsrc1 %f0, %f2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fsrc1s %f1, %f3 ! encoding: [0x87,0xb0,0x4e,0xa0]
+fsrc1s %f1, %f3
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fsrc2 %f0, %f2 ! encoding: [0x85,0xb0,0x0f,0x00]
+fsrc2 %f0, %f2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fsrc2s %f1, %f3 ! encoding: [0x87,0xb0,0x0f,0x21]
+fsrc2s %f1, %f3
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fnot1 %f0, %f2 ! encoding: [0x85,0xb0,0x0d,0x40]
+fnot1 %f0, %f2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fnot1s %f1, %f3 ! encoding: [0x87,0xb0,0x4d,0x60]
+fnot1s %f1, %f3
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fnot2 %f0, %f2 ! encoding: [0x85,0xb0,0x0c,0xc0]
+fnot2 %f0, %f2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fnot2s %f1, %f3 ! encoding: [0x87,0xb0,0x0c,0xe1]
+fnot2s %f1, %f3
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: for %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0f,0x82]
+for %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fors %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4f,0xa3]
+fors %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fnor %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0c,0x42]
+fnor %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fnors %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4c,0x63]
+fnors %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fand %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0e,0x02]
+fand %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fands %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4e,0x23]
+fands %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fnand %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0d,0xc2]
+fnand %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fnands %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4d,0xe3]
+fnands %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fxor %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0d,0x82]
+fxor %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fxors %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4d,0xa3]
+fxors %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fxnor %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0e,0x42]
+fxnor %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fxnors %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4e,0x63]
+fxnors %f1, %f3, %f5
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fornot1 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0f,0x42]
+fornot1 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fornot1s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4f,0x63]
+fornot1s %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fornot2 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0e,0xc2]
+fornot2 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fornot2s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4e,0xe3]
+fornot2s %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fandnot1 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0d,0x02]
+fandnot1 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fandnot1s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4d,0x23]
+fandnot1s %f1, %f3, %f5
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fandnot2 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x0c,0x82]
+fandnot2 %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fandnot2s %f1, %f3, %f5 ! encoding: [0x8b,0xb0,0x4c,0xa3]
+fandnot2s %f1, %f3, %f5
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fcmpgt16 %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x05,0x02]
+fcmpgt16 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fcmpgt32 %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x05,0x82]
+fcmpgt32 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fcmple16 %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x04,0x02]
+fcmple16 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fcmple32 %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x04,0x82]
+fcmple32 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fcmpne16 %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x04,0x42]
+fcmpne16 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fcmpne32 %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x04,0xc2]
+fcmpne32 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fcmpeq16 %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x05,0x42]
+fcmpeq16 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: fcmpeq32 %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x05,0xc2]
+fcmpeq32 %f0, %f2, %o0
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: edge8 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0x09]
+edge8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: edge8l %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0x49]
+edge8l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: edge16 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0x89]
+edge16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: edge16l %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0xc9]
+edge16l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: edge32 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x01,0x09]
+edge32 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: edge32l %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x01,0x49]
+edge32l %o0, %o1, %o2
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: pdist %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x07,0xc2]
+pdist %f0, %f2, %f4
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: array8 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x02,0x09]
+array8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: array16 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x02,0x49]
+array16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: array32 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x02,0x89]
+array32 %o0, %o1, %o2
+
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
+! VIS: shutdown ! encoding: [0x81,0xb0,0x10,0x00]
+shutdown
diff --git a/llvm/test/MC/Sparc/sparc-vis2.s b/llvm/test/MC/Sparc/sparc-vis2.s
new file mode 100644
index 0000000000000..3318884388562
--- /dev/null
+++ b/llvm/test/MC/Sparc/sparc-vis2.s
@@ -0,0 +1,55 @@
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS2
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis2 -show-encoding | FileCheck %s --check-prefixes=VIS2 --implicit-check-not=error:
+
+!! VIS 2 instructions.
+
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: bmask %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x03,0x29]
+bmask %o0, %o1, %o2
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: bshuffle %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x09,0x82]
+bshuffle %f0, %f2, %f4
+
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: siam 0 ! encoding: [0x81,0xb0,0x10,0x20]
+siam 0
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: siam 1 ! encoding: [0x81,0xb0,0x10,0x21]
+siam 1
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: siam 2 ! encoding: [0x81,0xb0,0x10,0x22]
+siam 2
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: siam 3 ! encoding: [0x81,0xb0,0x10,0x23]
+siam 3
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: siam 4 ! encoding: [0x81,0xb0,0x10,0x24]
+siam 4
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: siam 5 ! encoding: [0x81,0xb0,0x10,0x25]
+siam 5
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: siam 6 ! encoding: [0x81,0xb0,0x10,0x26]
+siam 6
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: siam 7 ! encoding: [0x81,0xb0,0x10,0x27]
+siam 7
+
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: edge8n %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0x29]
+edge8n %o0, %o1, %o2
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: edge8ln %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0x69]
+edge8ln %o0, %o1, %o2
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: edge16n %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0xa9]
+edge16n %o0, %o1, %o2
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: edge16ln %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0xe9]
+edge16ln %o0, %o1, %o2
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: edge32n %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x01,0x29]
+edge32n %o0, %o1, %o2
+! NO-VIS2: error: instruction requires a CPU feature not currently enabled
+! VIS2: edge32ln %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x01,0x69]
+edge32ln %o0, %o1, %o2
diff --git a/llvm/test/MC/Sparc/sparc-vis3.s b/llvm/test/MC/Sparc/sparc-vis3.s
new file mode 100644
index 0000000000000..ea189fb344767
--- /dev/null
+++ b/llvm/test/MC/Sparc/sparc-vis3.s
@@ -0,0 +1,133 @@
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS3
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis3 -show-encoding | FileCheck %s --check-prefixes=VIS3 --implicit-check-not=error:
+
+!! VIS 3 instructions.
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: addxc %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x02,0x29]
+addxc %o0, %o1, %o2
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: addxccc %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x02,0x69]
+addxccc %o0, %o1, %o2
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: cmask8 %o0 ! encoding: [0x81,0xb0,0x03,0x68]
+cmask8 %o0
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: cmask16 %o0 ! encoding: [0x81,0xb0,0x03,0xa8]
+cmask16 %o0
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: cmask32 %o0 ! encoding: [0x81,0xb0,0x03,0xe8]
+cmask32 %o0
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fchksm16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x08,0x82]
+fchksm16 %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fmean16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x08,0x02]
+fmean16 %f0, %f2, %f4
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fhadds %f1, %f3, %f5 ! encoding: [0x8b,0xa0,0x4c,0x23]
+fhadds %f1, %f3, %f5
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fhaddd %f0, %f2, %f4 ! encoding: [0x89,0xa0,0x0c,0x42]
+fhaddd %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fhsubs %f1, %f3, %f5 ! encoding: [0x8b,0xa0,0x4c,0xa3]
+fhsubs %f1, %f3, %f5
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fhsubd %f0, %f2, %f4 ! encoding: [0x89,0xa0,0x0c,0xc2]
+fhsubd %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: flcmps %fcc0, %f3, %f5 ! encoding: [0x81,0xb0,0xea,0x25]
+flcmps %fcc0, %f3, %f5
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: flcmpd %fcc0, %f2, %f4 ! encoding: [0x81,0xb0,0xaa,0x44]
+flcmpd %fcc0, %f2, %f4
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fnadds %f1, %f3, %f5 ! encoding: [0x8b,0xa0,0x4a,0x23]
+fnadds %f1, %f3, %f5
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fnaddd %f0, %f2, %f4 ! encoding: [0x89,0xa0,0x0a,0x42]
+fnaddd %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fnhadds %f1, %f3, %f5 ! encoding: [0x8b,0xa0,0x4e,0x23]
+fnhadds %f1, %f3, %f5
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fnhaddd %f0, %f2, %f4 ! encoding: [0x89,0xa0,0x0e,0x42]
+fnhaddd %f0, %f2, %f4
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fnmuls %f1, %f3, %f5 ! encoding: [0x8b,0xa0,0x4b,0x23]
+fnmuls %f1, %f3, %f5
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fnmuld %f0, %f2, %f4 ! encoding: [0x89,0xa0,0x0b,0x42]
+fnmuld %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fnsmuld %f1, %f3, %f4 ! encoding: [0x89,0xa0,0x4f,0x23]
+fnsmuld %f1, %f3, %f4
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fpadd64 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x08,0x42]
+fpadd64 %f0, %f2, %f4
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fsll16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x04,0x22]
+fsll16 %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fsrl16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x04,0x62]
+fsrl16 %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fsll32 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x04,0xa2]
+fsll32 %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fsrl32 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x04,0xe2]
+fsrl32 %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fslas16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x05,0x22]
+fslas16 %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fsra16 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x05,0x62]
+fsra16 %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fslas32 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x05,0xa2]
+fslas32 %f0, %f2, %f4
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: fsra32 %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x05,0xe2]
+fsra32 %f0, %f2, %f4
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: lzcnt %o0, %o1 ! encoding: [0x93,0xb0,0x02,0xe8]
+lzcnt %o0, %o1
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: movstosw %f0, %o0 ! encoding: [0x91,0xb0,0x22,0x60]
+movstosw %f0, %o0
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: movstouw %f0, %o0 ! encoding: [0x91,0xb0,0x22,0x20]
+movstouw %f0, %o0
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: movdtox %f0, %o0 ! encoding: [0x91,0xb0,0x22,0x00]
+movdtox %f0, %o0
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: movwtos %o0, %f0 ! encoding: [0x81,0xb0,0x23,0x28]
+movwtos %o0, %f0
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: movxtod %o0, %f0 ! encoding: [0x81,0xb0,0x23,0x08]
+movxtod %o0, %f0
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: pdistn %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x07,0xe2]
+pdistn %f0, %f2, %o0
+
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: umulxhi %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x02,0xc9]
+umulxhi %o0, %o1, %o2
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: xmulx %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x22,0xa9]
+xmulx %o0, %o1, %o2
+! NO-VIS3: error: instruction requires a CPU feature not currently enabled
+! VIS3: xmulxhi %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x22,0xc9]
+xmulxhi %o0, %o1, %o2
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