[llvm] [RISCV] Support Push/Pop with Xqci (PR #134191)

via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 2 19:06:53 PDT 2025


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

<details>
<summary>Changes</summary>

The `qc.c.mienter` and `qc.c.mienter.nest` instructions, broadly only save the argument and temporary registers. The exceptions are that they also save `fp` (`s0`) to construct a frame chain from the signal handler to the frame below, and they also save `ra`. They are designed this way so that (if needed) push and pop instructions can be used to save the callee-saved registers.

This patch implements this optimisation, constructing the following rather than a long sequence of `sw` and `lw` instructions for saving the callee-saved registers:

```asm
  qc.c.mienter
  qc.cm.push {ra, s0-sN}, -M
  ...
  qc.cm.pop {ra, s0-sN}, M
  qc.c.mileaveret
```

There are some carefully-worked-out details here, especially around CFI information. For any register saved by both `qc.c.mienter(.nest)` and the push (which is `ra` and `s0` at most), we point the CFI information at the version saved by `qc.c.mienter(.nest)`. This ensures the CFI points at the same `fp` copy as a frame pointer unwinder would find.

---

Patch is 133.22 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/134191.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+59-19) 
- (modified) llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll (+1919-266) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 7a68f2878880e..ec7b7af579c06 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -486,6 +486,18 @@ getPushOrLibCallsSavedInfo(const MachineFunction &MF,
     return PushOrLibCallsCSI;
 
   for (const auto &CS : CSI) {
+    if (RVFI->useQCIInterrupt(MF)) {
+      // Some registers are saved by both `QC.C.MIENTER(.NEST)` and
+      // `QC.CM.PUSH(FP)`. In these cases, prioritise the CFI info that points
+      // to the versions saved by `QC.C.MIENTER(.NEST)` which is what FP
+      // unwinding would use.
+      const auto *FII = llvm::find_if(FixedCSRFIQCIInterruptMap, [&](auto P) {
+        return P.first == CS.getReg();
+      });
+      if (FII != std::end(FixedCSRFIQCIInterruptMap))
+        continue;
+    }
+
     const auto *FII = llvm::find_if(
         FixedCSRFIMap, [&](MCPhysReg P) { return P == CS.getReg(); });
     if (FII != std::end(FixedCSRFIMap))
@@ -826,12 +838,12 @@ static bool isPop(unsigned Opcode) {
 }
 
 static unsigned getPushOpcode(RISCVMachineFunctionInfo::PushPopKind Kind,
-                              bool HasFP) {
+                              bool UpdateFP) {
   switch (Kind) {
   case RISCVMachineFunctionInfo::PushPopKind::StdExtZcmp:
     return RISCV::CM_PUSH;
   case RISCVMachineFunctionInfo::PushPopKind::VendorXqccmp:
-    return HasFP ? RISCV::QC_CM_PUSHFP : RISCV::QC_CM_PUSH;
+    return UpdateFP ? RISCV::QC_CM_PUSHFP : RISCV::QC_CM_PUSH;
   default:
     llvm_unreachable("Unhandled PushPopKind");
   }
@@ -872,7 +884,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   // Emit prologue for shadow call stack.
   emitSCSPrologue(MF, MBB, MBBI, DL);
 
-  auto FirstFrameSetup = MBBI;
+  // We keep track of the first instruction because it might be a
+  // `(QC.)CM.PUSH(FP)`, and we may need to adjust the immediate rather than
+  // inserting an `addi sp, sp, -N*16`
+  auto PossiblePush = MBBI;
 
   // Skip past all callee-saved register spill instructions.
   while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
@@ -949,22 +964,32 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   }
 
   if (RVFI->useQCIInterrupt(MF)) {
+    // The function starts with `QC.C.MIENTER(.NEST)`, so the `(QC.)CM.PUSH(FP)`
+    // could only be the next instruction.
+    PossiblePush = std::next(PossiblePush);
+
+    // Insert the CFI metadata before where we think the `(QC.)CM.PUSH(FP)`
+    // could be. The PUSH will also get its own CFI metadata for its own
+    // modifications, which should come after the PUSH.
     unsigned CFIIndex = MF.addFrameInst(
         MCCFIInstruction::cfiDefCfaOffset(nullptr, QCIInterruptPushAmount));
-    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+    BuildMI(MBB, PossiblePush, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex)
         .setMIFlag(MachineInstr::FrameSetup);
 
-    emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI, getQCISavedInfo(MF, CSI));
-  } else if (RVFI->isPushable(MF) && FirstFrameSetup != MBB.end() &&
-             isPush(FirstFrameSetup->getOpcode())) {
+    emitCFIForCSI<CFISaveRegisterEmitter>(MBB, PossiblePush,
+                                          getQCISavedInfo(MF, CSI));
+  }
+
+  if (RVFI->isPushable(MF) && PossiblePush != MBB.end() &&
+      isPush(PossiblePush->getOpcode())) {
     // Use available stack adjustment in push instruction to allocate additional
     // stack space. Align the stack size down to a multiple of 16. This is
     // needed for RVE.
     // FIXME: Can we increase the stack size to a multiple of 16 instead?
     uint64_t Spimm =
         std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
-    FirstFrameSetup->getOperand(1).setImm(Spimm);
+    PossiblePush->getOperand(1).setImm(Spimm);
     StackSize -= Spimm;
 
     unsigned CFIIndex = MF.addFrameInst(
@@ -1868,10 +1893,13 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
   if (RVFI->useQCIInterrupt(MF)) {
     RVFI->setQCIInterruptStackSize(QCIInterruptPushAmount);
-  } else if (RVFI->isPushable(MF)) {
+  }
+
+  if (RVFI->isPushable(MF)) {
     // Determine how many GPRs we need to push and save it to RVFI.
     unsigned PushedRegNum = getNumPushPopRegs(CSI);
-    if (PushedRegNum) {
+    unsigned PushMoreThan = RVFI->useQCIInterrupt(MF) ? 2 : 0;
+    if (PushedRegNum > PushMoreThan) {
       RVFI->setRVPushRegs(PushedRegNum);
       RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));
     }
@@ -1897,8 +1925,9 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
         CS.setFrameIdx(FrameIdx);
         continue;
       }
-      // TODO: QCI Interrupt + Push/Pop
-    } else if (RVFI->useSaveRestoreLibCalls(MF) || RVFI->isPushable(MF)) {
+    }
+
+    if (RVFI->useSaveRestoreLibCalls(MF) || RVFI->isPushable(MF)) {
       const auto *FII = llvm::find_if(
           FixedCSRFIMap, [&](MCPhysReg P) { return P == CS.getReg(); });
       unsigned RegNum = std::distance(std::begin(FixedCSRFIMap), FII);
@@ -1911,6 +1940,9 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
         else
           Offset = -int64_t(RegNum + 1) * Size;
 
+        if (RVFI->useQCIInterrupt(MF))
+          Offset -= QCIInterruptPushAmount;
+
         int FrameIdx = MFI.CreateFixedSpillStackObject(Size, Offset);
         assert(FrameIdx < 0);
         CS.setFrameIdx(FrameIdx);
@@ -1939,12 +1971,17 @@ bool RISCVFrameLowering::assignCalleeSavedSpillSlots(
     // because there are gaps which are reserved for future use.
     MFI.CreateFixedSpillStackObject(
         QCIInterruptPushAmount, -static_cast<int64_t>(QCIInterruptPushAmount));
-  } else if (RVFI->isPushable(MF)) {
+  }
+
+  if (RVFI->isPushable(MF)) {
     // Allocate a fixed object that covers all the registers that are pushed.
     if (unsigned PushedRegs = RVFI->getRVPushRegs()) {
       int64_t PushedRegsBytes =
           static_cast<int64_t>(PushedRegs) * (STI.getXLen() / 8);
-      MFI.CreateFixedSpillStackObject(PushedRegsBytes, -PushedRegsBytes);
+      int64_t QCIOffset =
+          RVFI->useQCIInterrupt(MF) ? QCIInterruptPushAmount : 0;
+      MFI.CreateFixedSpillStackObject(PushedRegsBytes,
+                                      -PushedRegsBytes - QCIOffset);
     }
   } else if (int LibCallRegs = getLibCallID(MF, CSI) + 1) {
     // Allocate a fixed object that covers all of the stack allocated by the
@@ -1982,13 +2019,15 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
 
     for (auto [Reg, _Offset] : FixedCSRFIQCIInterruptMap)
       MBB.addLiveIn(Reg);
-    // TODO: Handle QCI Interrupt + Push/Pop
-  } else if (RVFI->isPushable(*MF)) {
+  }
+
+  if (RVFI->isPushable(*MF)) {
     // Emit CM.PUSH with base SPimm & evaluate Push stack
     unsigned PushedRegNum = RVFI->getRVPushRegs();
     if (PushedRegNum > 0) {
       // Use encoded number to represent registers to spill.
-      unsigned Opcode = getPushOpcode(RVFI->getPushPopKind(*MF), hasFP(*MF));
+      unsigned Opcode = getPushOpcode(
+          RVFI->getPushPopKind(*MF), hasFP(*MF) && !RVFI->useQCIInterrupt(*MF));
       unsigned RegEnc = RISCVZC::encodeRlistNumRegs(PushedRegNum);
       MachineInstrBuilder PushBuilder =
           BuildMI(MBB, MI, DL, TII.get(Opcode))
@@ -2146,8 +2185,9 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters(
     // QC.C.MILEAVERET which we already inserted to return.
     assert(MI->getOpcode() == RISCV::QC_C_MILEAVERET &&
            "Unexpected QCI Interrupt Return Instruction");
-    // TODO: Handle QCI + Push/Pop
-  } else if (RVFI->isPushable(*MF)) {
+  }
+
+  if (RVFI->isPushable(*MF)) {
     unsigned PushedRegNum = RVFI->getRVPushRegs();
     if (PushedRegNum > 0) {
       unsigned Opcode = getPopOpcode(RVFI->getPushPopKind(*MF));
diff --git a/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll b/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
index 76d61eee07eef..94e3fad2b6ccd 100644
--- a/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+++ b/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
@@ -1,4 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
 ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint -o - %s \
 ; RUN:   -verify-machineinstrs | FileCheck --check-prefix=QCI %s
 
@@ -13,6 +14,14 @@
 ; RUN:   -o - %s -verify-machineinstrs \
 ; RUN:   | FileCheck --check-prefix=QCI-PUSH-POP %s
 
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint,+experimental-xqccmp \
+; RUN:   -o - %s -verify-machineinstrs \
+; RUN:   | FileCheck --check-prefix=QCI-QCCMP-PUSH-POP %s
+
+; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint,+experimental-xqccmp \
+; RUN:   -o - %s -verify-machineinstrs  -frame-pointer=all \
+; RUN:   | FileCheck --check-prefix=QCI-QCCMP-PUSH-POP-FP %s
+
 ;; This tests "interrupt"="qci-nest" and "interrupt"="qci-nonest" frame lowering.
 ;; including CFI information. These tests should all lack `nounwind`.
 ;;
@@ -91,6 +100,54 @@ define void @test_nest_empty() "interrupt"="qci-nest" {
 ; QCI-PUSH-POP-NEXT:    .cfi_offset t5, -76
 ; QCI-PUSH-POP-NEXT:    .cfi_offset t6, -80
 ; QCI-PUSH-POP-NEXT:    qc.c.mileaveret
+;
+; QCI-QCCMP-PUSH-POP-LABEL: test_nest_empty:
+; QCI-QCCMP-PUSH-POP:       # %bb.0:
+; QCI-QCCMP-PUSH-POP-NEXT:    qc.c.mienter.nest
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_def_cfa_offset 96
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset ra, -16
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t0, -24
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t1, -28
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t2, -32
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset s0, -8
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a0, -36
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a1, -40
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a2, -44
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a3, -48
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a4, -52
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a5, -56
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a6, -60
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a7, -64
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t3, -68
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t4, -72
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t5, -76
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t6, -80
+; QCI-QCCMP-PUSH-POP-NEXT:    qc.c.mileaveret
+;
+; QCI-QCCMP-PUSH-POP-FP-LABEL: test_nest_empty:
+; QCI-QCCMP-PUSH-POP-FP:       # %bb.0:
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    qc.c.mienter.nest
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa_offset 96
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset ra, -16
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t0, -24
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t1, -28
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t2, -32
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset s0, -8
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a0, -36
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a1, -40
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a2, -44
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a3, -48
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a4, -52
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a5, -56
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a6, -60
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a7, -64
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t3, -68
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t4, -72
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t5, -76
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t6, -80
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa s0, 0
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa sp, 96
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    qc.c.mileaveret
   ret void
 }
 
@@ -165,6 +222,54 @@ define void @test_nonest_empty() "interrupt"="qci-nonest" {
 ; QCI-PUSH-POP-NEXT:    .cfi_offset t5, -76
 ; QCI-PUSH-POP-NEXT:    .cfi_offset t6, -80
 ; QCI-PUSH-POP-NEXT:    qc.c.mileaveret
+;
+; QCI-QCCMP-PUSH-POP-LABEL: test_nonest_empty:
+; QCI-QCCMP-PUSH-POP:       # %bb.0:
+; QCI-QCCMP-PUSH-POP-NEXT:    qc.c.mienter
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_def_cfa_offset 96
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset ra, -16
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t0, -24
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t1, -28
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t2, -32
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset s0, -8
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a0, -36
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a1, -40
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a2, -44
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a3, -48
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a4, -52
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a5, -56
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a6, -60
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a7, -64
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t3, -68
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t4, -72
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t5, -76
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t6, -80
+; QCI-QCCMP-PUSH-POP-NEXT:    qc.c.mileaveret
+;
+; QCI-QCCMP-PUSH-POP-FP-LABEL: test_nonest_empty:
+; QCI-QCCMP-PUSH-POP-FP:       # %bb.0:
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    qc.c.mienter
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa_offset 96
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset ra, -16
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t0, -24
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t1, -28
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t2, -32
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset s0, -8
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a0, -36
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a1, -40
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a2, -44
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a3, -48
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a4, -52
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a5, -56
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a6, -60
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a7, -64
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t3, -68
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t4, -72
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t5, -76
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t6, -80
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa s0, 0
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa sp, 96
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    qc.c.mileaveret
   ret void
 }
 
@@ -257,6 +362,64 @@ define void @test_nest_asm() "interrupt"="qci-nest" {
 ; QCI-PUSH-POP-NEXT:    #NO_APP
 ; QCI-PUSH-POP-NEXT:    call use_i32
 ; QCI-PUSH-POP-NEXT:    qc.c.mileaveret
+;
+; QCI-QCCMP-PUSH-POP-LABEL: test_nest_asm:
+; QCI-QCCMP-PUSH-POP:       # %bb.0:
+; QCI-QCCMP-PUSH-POP-NEXT:    qc.c.mienter.nest
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_def_cfa_offset 96
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset ra, -16
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t0, -24
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t1, -28
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t2, -32
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset s0, -8
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a0, -36
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a1, -40
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a2, -44
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a3, -48
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a4, -52
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a5, -56
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a6, -60
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a7, -64
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t3, -68
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t4, -72
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t5, -76
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t6, -80
+; QCI-QCCMP-PUSH-POP-NEXT:    li a0, 1
+; QCI-QCCMP-PUSH-POP-NEXT:    #APP
+; QCI-QCCMP-PUSH-POP-NEXT:    # a0 <- a0
+; QCI-QCCMP-PUSH-POP-NEXT:    #NO_APP
+; QCI-QCCMP-PUSH-POP-NEXT:    call use_i32
+; QCI-QCCMP-PUSH-POP-NEXT:    qc.c.mileaveret
+;
+; QCI-QCCMP-PUSH-POP-FP-LABEL: test_nest_asm:
+; QCI-QCCMP-PUSH-POP-FP:       # %bb.0:
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    qc.c.mienter.nest
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa_offset 96
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset ra, -16
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t0, -24
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t1, -28
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t2, -32
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset s0, -8
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a0, -36
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a1, -40
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a2, -44
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a3, -48
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a4, -52
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a5, -56
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a6, -60
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a7, -64
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t3, -68
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t4, -72
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t5, -76
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t6, -80
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa s0, 0
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    li a0, 1
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    #APP
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    # a0 <- a0
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    #NO_APP
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    call use_i32
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa sp, 96
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    qc.c.mileaveret
   %1 = call i32 asm sideeffect "/* $0 <- $1 */", "=r,r"(i32 1)
   call void @use_i32(i32 %1)
   ret void
@@ -348,6 +511,64 @@ define void @test_nonest_asm() "interrupt"="qci-nonest" {
 ; QCI-PUSH-POP-NEXT:    #NO_APP
 ; QCI-PUSH-POP-NEXT:    call use_i32
 ; QCI-PUSH-POP-NEXT:    qc.c.mileaveret
+;
+; QCI-QCCMP-PUSH-POP-LABEL: test_nonest_asm:
+; QCI-QCCMP-PUSH-POP:       # %bb.0:
+; QCI-QCCMP-PUSH-POP-NEXT:    qc.c.mienter
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_def_cfa_offset 96
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset ra, -16
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t0, -24
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t1, -28
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t2, -32
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset s0, -8
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a0, -36
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a1, -40
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a2, -44
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a3, -48
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a4, -52
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a5, -56
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a6, -60
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset a7, -64
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t3, -68
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t4, -72
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t5, -76
+; QCI-QCCMP-PUSH-POP-NEXT:    .cfi_offset t6, -80
+; QCI-QCCMP-PUSH-POP-NEXT:    li a0, 1
+; QCI-QCCMP-PUSH-POP-NEXT:    #APP
+; QCI-QCCMP-PUSH-POP-NEXT:    # a0 <- a0
+; QCI-QCCMP-PUSH-POP-NEXT:    #NO_APP
+; QCI-QCCMP-PUSH-POP-NEXT:    call use_i32
+; QCI-QCCMP-PUSH-POP-NEXT:    qc.c.mileaveret
+;
+; QCI-QCCMP-PUSH-POP-FP-LABEL: test_nonest_asm:
+; QCI-QCCMP-PUSH-POP-FP:       # %bb.0:
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    qc.c.mienter
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa_offset 96
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset ra, -16
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t0, -24
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t1, -28
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t2, -32
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset s0, -8
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a0, -36
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a1, -40
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a2, -44
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a3, -48
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a4, -52
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a5, -56
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a6, -60
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset a7, -64
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t3, -68
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t4, -72
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t5, -76
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_offset t6, -80
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa s0, 0
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    li a0, 1
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    #APP
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    # a0 <- a0
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    #NO_APP
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    call use_i32
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    .cfi_def_cfa sp, 96
+; QCI-QCCMP-PUSH-POP-FP-NEXT:    qc.c.mileaveret
   %1 = call i32 asm sideeffect "/* $0 <- $1 */", "...
[truncated]

``````````

</details>


https://github.com/llvm/llvm-project/pull/134191


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