[llvm] [LLVM][AArch64] Refactor lowering of fixed length integer setcc operations. (PR #132434)

[Eli Friedman via llvm-commits]

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@@ -25268,6 +25216,14 @@ static SDValue performSETCCCombine(SDNode *N,
   if (SDValue V = performOrXorChainCombine(N, DAG))
     return V;
 
+  EVT CmpVT = LHS.getValueType();
+
+  APInt SplatLHSVal;
+  if (CmpVT.isInteger() && Cond == ISD::SETGT &&
+      ISD::isConstantSplatVector(LHS.getNode(), SplatLHSVal) &&
+      SplatLHSVal.isOne())
+    return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, CmpVT), RHS, ISD::SETGE);
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efriedma-quic wrote:

Probably worth adding a comment explaining why you can't currently use a TableGen pattern for this.  But seems fine.

https://github.com/llvm/llvm-project/pull/132434