[llvm] [AMDGPU] (xor (cmp_eq x, 1), -1) -> cmp_neq x, 1 (PR #133698)

[Pierre van Houtryve via llvm-commits]

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@@ -15,34 +15,39 @@ define void @nested_inf_loop(i1 %0, i1 %1) {
 ; OPT-NEXT:    ret void
 ;
 ; ISA-LABEL: nested_inf_loop:
-; ISA-NEXT: %bb.0:                                ; %BB
-; ISA-NEXT: 	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; ISA-NEXT: 	v_and_b32_e32 v1, 1, v1
-; ISA-NEXT: 	v_and_b32_e32 v0, 1, v0
-; ISA-NEXT: 	v_cmp_eq_u32_e64 s[4:5], 1, v1
-; ISA-NEXT: 	v_cmp_eq_u32_e32 vcc, 1, v0
-; ISA-NEXT: 	s_xor_b64 s[6:7], vcc, -1
-; ISA-NEXT: 	s_mov_b64 s[8:9], 0
-; ISA-NEXT: .LBB0_1:                                ; %BB1
-; ISA: 	      s_and_b64 s[10:11], exec, s[6:7]
-; ISA-NEXT: 	s_or_b64 s[8:9], s[10:11], s[8:9]
-; ISA-NEXT: 	s_andn2_b64 exec, exec, s[8:9]
-; ISA-NEXT: 	s_cbranch_execnz .LBB0_1
-; ISA-NEXT: %bb.2:                                ; %BB2
-; ISA: 	      s_or_b64 exec, exec, s[8:9]
-; ISA-NEXT: 	s_mov_b64 s[8:9], 0
-; ISA-NEXT: .LBB0_3:                                ; %BB4
-; ISA: 	      s_and_b64 s[10:11], exec, s[4:5]
-; ISA-NEXT: 	s_or_b64 s[8:9], s[10:11], s[8:9]
-; ISA-NEXT: 	s_andn2_b64 exec, exec, s[8:9]
-; ISA-NEXT: 	s_cbranch_execnz .LBB0_3
-; ISA-NEXT: %bb.4:                                ; %loop.exit.guard
-; ISA: 	      s_or_b64 exec, exec, s[8:9]
-; ISA-NEXT: 	s_mov_b64 vcc, 0
-; ISA-NEXT: 	s_mov_b64 s[8:9], 0
-; ISA-NEXT: 	s_branch .LBB0_1
-; ISA-NEXT: %bb.5:                                ; %DummyReturnBlock
-; ISA-NEXT: 	s_setpc_b64 s[30:31]
+; ISA:       ; %bb.0: ; %BB
----------------
Pierre-vh wrote:

It looks like this test wasn't autogenerated properly before, can you precommit an update to it?
Otherwise it's difficult to tell what changed.

https://github.com/llvm/llvm-project/pull/133698