[llvm] [LLVM][CodeGen][SVE] Prefer NEON instructions when zeroing Z registers. (PR #133929)

[Paul Walker via llvm-commits]

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@@ -7714,6 +7714,7 @@ def MOVIv2d_ns   : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128,
                                                 "movi", ".2d",
                    [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
 
+let Predicates = [HasNEON] in {
 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
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paulwalker-arm wrote:

Yes, the fixed length spat/build vector would have been legalised so that it cannot get this far.  I figured since I was protecting the code for scalable vector types I may as well just protect the whole related block.

https://github.com/llvm/llvm-project/pull/133929