[llvm] ba7feaa - [AMDGPU][Docs] Fix and update AMDGPUUsage.rst (#133894)
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Tue Apr 1 04:59:46 PDT 2025
Author: Mirko BrkuĊĦanin
Date: 2025-04-01T13:59:42+02:00
New Revision: ba7feaab92ca807419de6f2b80dda2a1d1759d97
URL: https://github.com/llvm/llvm-project/commit/ba7feaab92ca807419de6f2b80dda2a1d1759d97
DIFF: https://github.com/llvm/llvm-project/commit/ba7feaab92ca807419de6f2b80dda2a1d1759d97.diff
LOG: [AMDGPU][Docs] Fix and update AMDGPUUsage.rst (#133894)
- Fix notes about SALU float and src1 SGPRs for dpp instructions
- Add split between gfx11 and gfx12 sections, update references.
Added:
Modified:
llvm/docs/AMDGPUUsage.rst
Removed:
################################################################################
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index ab507e3714ebb..d1535960a0257 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -515,6 +515,8 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
work-item Add product
IDs names.
+ **GCN GFX12 (RDNA 4)** [AMD-GCN-GFX12-RDNA4]_
+ -----------------------------------------------------------------------------------------------------------------------
``gfx1200`` ``amdgcn`` dGPU - cumode - Architected *TBA*
- wavefrontsize64 flat
scratch .. TODO::
@@ -619,18 +621,18 @@ Generic processor code objects are versioned. See :ref:`amdgpu-generic-processor
SALU floating point instructions
are not available on:
- - ``gfx1150``
- - ``gfx1151``
- - ``gfx1152``
- - ``gfx1153``
+ - ``gfx1100``
+ - ``gfx1101``
+ - ``gfx1102``
+ - ``gfx1103``
SGPRs are not supported for src1
in dpp instructions for:
- - ``gfx1150``
- - ``gfx1151``
- - ``gfx1152``
- - ``gfx1153``
+ - ``gfx1100``
+ - ``gfx1101``
+ - ``gfx1102``
+ - ``gfx1103``
``gfx12-generic`` ``amdgcn`` - ``gfx1200`` - wavefrontsize64 - Architected No restrictions.
@@ -17618,7 +17620,7 @@ combinations of operands, refer to one of instruction set architecture manuals
[AMD-GCN-GFX900-GFX904-VEGA]_, [AMD-GCN-GFX906-VEGA7NM]_,
[AMD-GCN-GFX908-CDNA1]_, [AMD-GCN-GFX90A-CDNA2]_,
[AMD-GCN-GFX942-CDNA3]_, [AMD-GCN-GFX10-RDNA1]_, [AMD-GCN-GFX10-RDNA2]_,
-[AMD-GCN-GFX11-RDNA3]_ and [AMD-GCN-GFX11-RDNA3.5]_.
+[AMD-GCN-GFX11-RDNA3]_, [AMD-GCN-GFX11-RDNA3.5]_ and [AMD-GCN-GFX12-RDNA4]_.
Operands
~~~~~~~~
@@ -18420,6 +18422,7 @@ Additional Documentation
.. [AMD-GCN-GFX10-RDNA2] `AMD RDNA 2 Instruction Set Architecture <https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf>`__
.. [AMD-GCN-GFX11-RDNA3] `AMD RDNA 3 Instruction Set Architecture <https://developer.amd.com/wp-content/resources/RDNA3_Shader_ISA_December2022.pdf>`__
.. [AMD-GCN-GFX11-RDNA3.5] `AMD RDNA 3.5 Instruction Set Architecture <https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna35_instruction_set_architecture.pdf>`__
+.. [AMD-GCN-GFX12-RDNA4] `AMD RDNA 4 Instruction Set Architecture <https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna4-instruction-set-architecture.pdf>`__
.. [AMD-RADEON-HD-2000-3000] `AMD R6xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf>`__
.. [AMD-RADEON-HD-4000] `AMD R7xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf>`__
.. [AMD-RADEON-HD-5000] `AMD Evergreen shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf>`__
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