[llvm] ea68b22 - [RISCV] Prevent disassembling RVC hint instructions with x16-x31 for RVE. (#133805)
via llvm-commits
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Mon Mar 31 20:49:54 PDT 2025
Author: Craig Topper
Date: 2025-03-31T20:49:51-07:00
New Revision: ea68b228816dfbe27f3e1ba1149116587758d56c
URL: https://github.com/llvm/llvm-project/commit/ea68b228816dfbe27f3e1ba1149116587758d56c
DIFF: https://github.com/llvm/llvm-project/commit/ea68b228816dfbe27f3e1ba1149116587758d56c.diff
LOG: [RISCV] Prevent disassembling RVC hint instructions with x16-x31 for RVE. (#133805)
We can't ignore the return value form the GPR decode function, as it
contains the RVE check.
Added:
Modified:
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/test/MC/RISCV/rve-invalid.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index cda34ac01d7c0..4e6d2b642c4ce 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -523,13 +523,13 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
- [[maybe_unused]] DecodeStatus Result =
- DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
- assert(Result == MCDisassembler::Success && "Invalid register");
+ if (!Check(S, DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(Inst.getOperand(0));
Inst.addOperand(MCOperand::createImm(0));
- return MCDisassembler::Success;
+ return S;
}
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
@@ -569,34 +569,44 @@ decodeRVCInstrRdRs1UImmLog2XLenNonZero(MCInst &Inst, uint32_t Insn,
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
- DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
- DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
- return MCDisassembler::Success;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder)))
+ return MCDisassembler::Fail;
+ return S;
}
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
- DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ return MCDisassembler::Fail;
Inst.addOperand(Inst.getOperand(0));
- DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
- return MCDisassembler::Success;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder)))
+ return MCDisassembler::Fail;
+ return S;
}
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
+ DecodeStatus S = MCDisassembler::Success;
uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
- DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
- DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
- DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder)))
+ return MCDisassembler::Fail;
+ if (!Check(S, DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder)))
+ return MCDisassembler::Fail;
[[maybe_unused]] DecodeStatus Result =
decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
assert(Result == MCDisassembler::Success && "Invalid immediate");
@@ -610,7 +620,7 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
else
Inst.addOperand(MCOperand::createImm(4));
- return MCDisassembler::Success;
+ return S;
}
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
diff --git a/llvm/test/MC/RISCV/rve-invalid.s b/llvm/test/MC/RISCV/rve-invalid.s
index 95dc156f250a3..0b1e8961dc89d 100644
--- a/llvm/test/MC/RISCV/rve-invalid.s
+++ b/llvm/test/MC/RISCV/rve-invalid.s
@@ -1,16 +1,17 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+e < %s 2>&1 | FileCheck %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \
-# RUN: | llvm-objdump --mattr=+e -M no-aliases -d -r - \
+# RUN: not llvm-mc -triple riscv32 -mattr=+e,+zca < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zca < %s \
+# RUN: | llvm-objdump --mattr=+e,+zca -M no-aliases -d -r - \
# RUN: | FileCheck -check-prefix=CHECK-DIS %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 | FileCheck %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \
-# RUN: | llvm-objdump --mattr=+e -M no-aliases -d -r - \
+# RUN: not llvm-mc -triple riscv64 -mattr=+e,+zca < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zca < %s \
+# RUN: | llvm-objdump --mattr=+e,+zca -M no-aliases -d -r - \
# RUN: | FileCheck -check-prefix=CHECK-DIS %s
# Perform a simple check that registers x16-x31 (and the equivalent ABI names)
# are rejected for RV32E/RV64E, when both assembling and disassembling.
-
+.option push
+.option exact
# CHECK-DIS: 00001837 <unknown>
# CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction
lui x16, 1
@@ -108,3 +109,14 @@ auipc t5, 31
# CHECK-DIS: 00020f97 <unknown>
# CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction
auipc t6, 32
+.option pop
+
+# CHECK-DIS: 0f81 <unknown>
+# CHECK: :[[@LINE+1]]:8: error: register must be a GPR excluding zero (x0)
+c.addi x31, 0
+# CHECK-DIS: 9846 <unknown>
+# CHECK: :[[@LINE+1]]:7: error: register must be a GPR excluding zero (x0)
+c.add x16, x17
+# CHECK-DIS: 8046 <unknown>
+# CHECK: :[[@LINE+1]]:10: error: register must be a GPR excluding zero (x0)
+c.mv x0, x17
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