[llvm] [AMDGPU] Fix SIFoldOperandsImpl::tryFoldZeroHighBits when met non-reg src1 operand. (PR #133761)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,15 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1101 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s
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arsenm wrote:

Can this be merged into high-bits-zeroed-16-bit-ops.mir

https://github.com/llvm/llvm-project/pull/133761