[llvm] [RISCV] Prevent disassembling RVC hint instructions with x16-x31 for RVE. (PR #133805)

[Sam Elliott via llvm-commits]

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@@ -108,3 +109,14 @@ auipc t5, 31
 # CHECK-DIS: 00020f97 <unknown>
 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction
 auipc t6, 32
+.option pop
+
+# CHECK-DIS: 0f81 <unknown>
+# CHECK: :[[@LINE+1]]:8: error: register must be a GPR excluding zero (x0)
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lenary wrote:

Sorry!

https://github.com/llvm/llvm-project/pull/133805