[llvm] GlobalISel: neg (and x, 1) --> SIGN_EXTEND_INREG x, 1 (PR #131367)

[Matthias Braun via llvm-commits]

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@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -o - -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner %s | FileCheck %s
+---
+name: test_combine_neg_and_one_to_sext_inreg_v2i32
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MatzeB wrote:

It's a generic combine rule not tied to a target. Given that people wanted to see scalar and vectorized versions I wondered whether people maybe also wanted to see two targets especially given that for aarch64 the combine isn't really helpful in the vectorized version[1]

Anyway moved the test to AArch64 now.

[1] The combine helps scalar AArch64 because G_SEXT_INREG can be implement with an `sbfx` instruction; for the vectorized case a `G_SEXT_INREG` will just be broken to two instructions (`SHL` + `SHRS`) which isn't really helpful (and hopefully doesn't hurt). Unfortunately as far as I can tell, the GlobalISel legalization interface however does not provide enough information for the target to differentiate between those two cases.



https://github.com/llvm/llvm-project/pull/131367