[llvm] [AMDGPU] Support block load/store for CSR (PR #130013)

[Diana Picus via llvm-commits]

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@@ -566,6 +576,13 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction,
   // frame, so save it here and add it to the RegScavenger later.
   std::optional<int> ScavengeFI;
 
+  // Map each VGPR CSR to the mask needed to save and restore it using block
+  // load/store instructions. Only used if the subtarget feature for VGPR block
+  // load/store is enabled.
+  // This is only useful during prolog/epilog insertion, so it doesn't need to
+  // be serialized.
+  IndexedMap<uint32_t, VGPRBlock2IndexFunctor> MaskForVGPRBlockOps;
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rovka wrote:

Actually that comment is obsolete, we also use this when printing out the assembly (so we can put the comment about which regs might be getting spilled). It's difficult to add this to the instructions because the mask is first computed in assignCalleeSavedSpillSlots, which doesn't create any instructions yet.

https://github.com/llvm/llvm-project/pull/130013