[lld] [lld][LoongArch] Convert TLS IE to LE in the normal or medium code model (PR #123680)
Zhaoxin Yang via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 31 03:57:37 PDT 2025
https://github.com/ylzsx updated https://github.com/llvm/llvm-project/pull/123680
>From 9d29d9bbeb0695ec90e79017ed0fd420c073e47e Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Tue, 31 Dec 2024 15:51:43 +0800
Subject: [PATCH 1/9] Relax TLSDESC code sequence.
Original code sequence:
* pcalau12i $a0, %desc_pc_hi20(sym_desc)
* addi.d $a0, $a0, %desc_pc_lo12(sym_desc)
* ld.d $ra, $a0, %desc_ld(sym_desc)
* jirl $ra, $ra, %desc_call(sym_desc)
Cannot convert to LE/IE, but relax:
* pcaddi $a0, %desc_pcrel_20(sym_desc)
* ld.d $ra, $a0, %desc_ld(sym_desc)
* jirl $ra, $ra, %desc_call(sym_desc)
TODO: The conversion of TLSDESC GD/LD to LE/IE will implement in a
future patch.
---
lld/ELF/Arch/LoongArch.cpp | 19 +-
lld/test/ELF/loongarch-relax-tlsdesc.s | 280 +++++++++++++++++++++++++
2 files changed, 297 insertions(+), 2 deletions(-)
create mode 100644 lld/test/ELF/loongarch-relax-tlsdesc.s
diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp
index 709b31ed4e01a..4edc625b05cb0 100644
--- a/lld/ELF/Arch/LoongArch.cpp
+++ b/lld/ELF/Arch/LoongArch.cpp
@@ -766,9 +766,12 @@ static bool isPairRelaxable(ArrayRef<Relocation> relocs, size_t i) {
// Relax code sequence.
// From:
// pcalau12i $a0, %pc_hi20(sym) | %ld_pc_hi20(sym) | %gd_pc_hi20(sym)
+// | %desc_pc_hi20(sym)
// addi.w/d $a0, $a0, %pc_lo12(sym) | %got_pc_lo12(sym) | %got_pc_lo12(sym)
+// | %desc_pc_lo12(sym)
// To:
-// pcaddi $a0, %pc_lo12(sym) | %got_pc_lo12(sym) | %got_pc_lo12(sym)
+// pcaddi $a0, %pc_lo12(sym) | %got_pc_lo12(sym) | %got_pc_lo12(sym)
+// | %desc_pcrel_20(sym)
//
// From:
// pcalau12i $a0, %got_pc_hi20(sym_got)
@@ -786,7 +789,9 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection &sec, size_t i,
(rHi20.type == R_LARCH_TLS_GD_PC_HI20 &&
rLo12.type == R_LARCH_GOT_PC_LO12) ||
(rHi20.type == R_LARCH_TLS_LD_PC_HI20 &&
- rLo12.type == R_LARCH_GOT_PC_LO12)))
+ rLo12.type == R_LARCH_GOT_PC_LO12) ||
+ (rHi20.type == R_LARCH_TLS_DESC_PC_HI20 &&
+ rLo12.type == R_LARCH_TLS_DESC_PC_LO12)))
return;
// GOT references to absolute symbols can't be relaxed to use pcaddi in
@@ -808,6 +813,8 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection &sec, size_t i,
dest = rHi20.sym->getVA(ctx);
else if (rHi20.expr == RE_LOONGARCH_TLSGD_PAGE_PC)
dest = ctx.in.got->getGlobalDynAddr(*rHi20.sym);
+ else if (rHi20.expr == RE_LOONGARCH_TLSDESC_PAGE_PC)
+ dest = ctx.in.got->getTlsDescAddr(*rHi20.sym);
else {
Err(ctx) << getErrorLoc(ctx, (const uint8_t *)loc) << "unknown expr ("
<< rHi20.expr << ") against symbol " << rHi20.sym
@@ -841,6 +848,8 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection &sec, size_t i,
sec.relaxAux->relocTypes[i + 2] = R_LARCH_TLS_GD_PCREL20_S2;
else if (rHi20.type == R_LARCH_TLS_LD_PC_HI20)
sec.relaxAux->relocTypes[i + 2] = R_LARCH_TLS_LD_PCREL20_S2;
+ else if (rHi20.type == R_LARCH_TLS_DESC_PC_HI20)
+ sec.relaxAux->relocTypes[i + 2] = R_LARCH_TLS_DESC_PCREL20_S2;
else
sec.relaxAux->relocTypes[i + 2] = R_LARCH_PCREL20_S2;
sec.relaxAux->writes.push_back(insn(PCADDI, getD5(nextInsn), 0, 0));
@@ -947,6 +956,7 @@ static bool relax(Ctx &ctx, InputSection &sec) {
case R_LARCH_GOT_PC_HI20:
case R_LARCH_TLS_GD_PC_HI20:
case R_LARCH_TLS_LD_PC_HI20:
+ case R_LARCH_TLS_DESC_PC_HI20:
// The overflow check for i+2 will be carried out in isPairRelaxable.
if (isPairRelaxable(relocs, i))
relaxPCHi20Lo12(ctx, sec, i, loc, r, relocs[i + 2], remove);
@@ -1081,6 +1091,11 @@ void LoongArch::finalizeRelax(int passes) const {
write32le(p, aux.writes[writesIdx++]);
r.expr = R_TLSGD_PC;
break;
+ case R_LARCH_TLS_DESC_PCREL20_S2:
+ skip = 4;
+ write32le(p, aux.writes[writesIdx++]);
+ r.expr = R_TLSDESC_PC;
+ break;
default:
llvm_unreachable("unsupported type");
}
diff --git a/lld/test/ELF/loongarch-relax-tlsdesc.s b/lld/test/ELF/loongarch-relax-tlsdesc.s
new file mode 100644
index 0000000000000..f9d984ad6387a
--- /dev/null
+++ b/lld/test/ELF/loongarch-relax-tlsdesc.s
@@ -0,0 +1,280 @@
+# REQUIRES: loongarch
+# RUN: rm -rf %t && split-file %s %t && cd %t
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 -mattr=+relax a.s -o a.64.o
+# RUN: llvm-mc -filetype=obj -triple=loongarch64 -mattr=+relax c.s -o c.64.o
+# RUN: ld.lld --relax -shared -soname=c.64.so c.64.o -o c.64.so
+
+## Test the TLSDESC relaxation.
+# RUN: ld.lld --relax -shared -z now a.64.o c.64.o -o a.64.so
+# RUN: llvm-readobj -r -x .got a.64.so | FileCheck --check-prefix=GD64-RELA %s
+# RUN: llvm-objdump --no-show-raw-insn -dr -h a.64.so | FileCheck %s --check-prefix=GD64
+
+## FIXME: The transition frome TLSDESC to IE/LE has not yet been implemented.
+## Keep the dynamic relocations and hand them over to dynamic linker.
+
+# RUN: ld.lld --relax -e 0 -z now a.64.o c.64.o -o a.64.le
+# RUN: llvm-readobj -r -x .got a.64.le | FileCheck --check-prefix=LE64-RELA %s
+# RUN: llvm-objdump --no-show-raw-insn -d -h a.64.le | FileCheck %s --check-prefix=LE64
+
+# RUN: ld.lld --no-relax -e 0 -z now a.64.o c.64.o -o a.64.le.norelax
+# RUN: llvm-objdump --no-show-raw-insn -d -h a.64.le.norelax | FileCheck %s --check-prefix=LE64-NORELAX
+
+# RUN: ld.lld --relax -e 0 -z now a.64.o c.64.so -o a.64.ie
+# RUN: llvm-readobj -r -x .got a.64.ie | FileCheck --check-prefix=IE64-RELA %s
+# RUN: llvm-objdump --no-show-raw-insn -d -h a.64.ie | FileCheck %s --check-prefix=IE64
+
+# RUN: ld.lld --no-relax -e 0 -z now a.64.o c.64.so -o a.64.ie.norelax
+# RUN: llvm-objdump --no-show-raw-insn -d -h a.64.ie.norelax | FileCheck %s --check-prefix=IE64-NORELAX
+
+# GD64-RELA: .rela.dyn {
+# GD64-RELA-NEXT: 0x20460 R_LARCH_TLS_DESC64 - 0x7FF
+# GD64-RELA-NEXT: 0x20430 R_LARCH_TLS_DESC64 a 0x0
+# GD64-RELA-NEXT: 0x20440 R_LARCH_TLS_DESC64 c 0x0
+# GD64-RELA-NEXT: 0x20450 R_LARCH_TLS_DESC64 d 0x0
+# GD64-RELA-NEXT: }
+# GD64-RELA: Hex dump of section '.got':
+# GD64-RELA-NEXT: 0x00020430 00000000 00000000 00000000 00000000 .
+# GD64-RELA-NEXT: 0x00020440 00000000 00000000 00000000 00000000 .
+# GD64-RELA-NEXT: 0x00020450 00000000 00000000 00000000 00000000 .
+# GD64-RELA-NEXT: 0x00020460 00000000 00000000 00000000 00000000 .
+
+# GD64: .got 00000040 0000000000020430
+
+## &.got[a]-. = 0x20430 - 0x10318 = 16454<<2
+# GD64: 10318: pcaddi $a0, 16454
+# GD64-NEXT: ld.d $ra, $a0, 0
+# GD64-NEXT: jirl $ra, $ra, 0
+# GD64-NEXT: add.d $a1, $a0, $tp
+
+## &.got[b]-. = 0x20430+48 - 0x10328: 0x10 pages, page offset 0x460
+## R_LARCH_RELAX does not appear in pairs. No relaxation.
+# GD64: 10328: pcalau12i $a0, 16
+# GD64-NEXT: addi.d $a0, $a0, 1120
+# GD64-NEXT: ld.d $ra, $a0, 0
+# GD64-NEXT: jirl $ra, $ra, 0
+# GD64-NEXT: add.d $a2, $a0, $tp
+
+## &.got[c]-. = 0x20430+16 - 0x1033c: 0x10 pages, page offset 0x440
+## Without R_LARCH_RELAX relocation. No relaxation.
+# GD64: 1033c: pcalau12i $a0, 16
+# GD64-NEXT: addi.d $t0, $zero, 0
+# GD64-NEXT: addi.d $a0, $a0, 1088
+# GD64-NEXT: addi.d $t0, $t0, 1
+# GD64-NEXT: ld.d $ra, $a0, 0
+# GD64-NEXT: addi.d $t0, $t0, 1
+# GD64-NEXT: jirl $ra, $ra, 0
+# GD64-NEXT: add.d $a3, $a0, $tp
+
+## &.got[d]-. = 0x20430+32 - 0x1035c = 16445<<2
+# GD64: 1035c: pcaddi $a0, 16445
+# GD64-NEXT: ld.d $ra, $a0, 0
+# GD64-NEXT: jirl $ra, $ra, 0
+# GD64-NEXT: add.d $a4, $a0, $tp
+
+# LE64-RELA: .rela.dyn {
+# LE64-RELA-NEXT: 0x30280 R_LARCH_TLS_DESC64 - 0x8
+# LE64-RELA-NEXT: 0x30290 R_LARCH_TLS_DESC64 - 0x800
+# LE64-RELA-NEXT: 0x302A0 R_LARCH_TLS_DESC64 - 0x1000
+# LE64-RELA-NEXT: 0x302B0 R_LARCH_TLS_DESC64 - 0x7FF
+# LE64-RELA-NEXT: }
+# LE64-RELA: Hex dump of section '.got':
+# LE64-RELA-NEXT: 0x00030280 00000000 00000000 00000000 00000000 .
+# LE64-RELA-NEXT: 0x00030290 00000000 00000000 00000000 00000000 .
+# LE64-RELA-NEXT: 0x000302a0 00000000 00000000 00000000 00000000 .
+# LE64-RELA-NEXT: 0x000302b0 00000000 00000000 00000000 00000000 .
+
+# LE64: .got 00000040 0000000000030280
+
+## &.got[a]-. = 0x30280 - 0x20228 = 16406<<2
+# LE64: 20228: pcaddi $a0, 16406
+# LE64-NEXT: ld.d $ra, $a0, 0
+# LE64-NEXT: jirl $ra, $ra, 0
+# LE64-NEXT: add.d $a1, $a0, $tp
+
+## &.got[b]-. = 0x30280+48 - 0x20238: 0x10 pages, page offset 0x2b0
+## R_LARCH_RELAX does not appear in pairs. No relaxation.
+# LE64: 20238: pcalau12i $a0, 16
+# LE64-NEXT: addi.d $a0, $a0, 688
+# LE64-NEXT: ld.d $ra, $a0, 0
+# LE64-NEXT: jirl $ra, $ra, 0
+# LE64-NEXT: add.d $a2, $a0, $tp
+
+## &.got[c]-. = 0x30280+16 - 0x2024c: 0x10 pages, page offset 0x290
+## Without R_LARCH_RELAX relocation. No relaxation.
+# LE64: 2024c: pcalau12i $a0, 16
+# LE64-NEXT: addi.d $t0, $zero, 0
+# LE64-NEXT: addi.d $a0, $a0, 656
+# LE64-NEXT: addi.d $t0, $t0, 1
+# LE64-NEXT: ld.d $ra, $a0, 0
+# LE64-NEXT: addi.d $t0, $t0, 1
+# LE64-NEXT: jirl $ra, $ra, 0
+# LE64-NEXT: add.d $a3, $a0, $tp
+
+## &.got[d]-. = 0x30280+32 - 0x2026c = 16397<<2
+# LE64: 2026c: pcaddi $a0, 16397
+# LE64-NEXT: ld.d $ra, $a0, 0
+# LE64-NEXT: jirl $ra, $ra, 0
+# LE64-NEXT: add.d $a4, $a0, $tp
+
+# LE64-NORELAX: .got 00000040 0000000000030288
+
+## &.got[a]-. = 0x30288 - 0x20228 = 0x10 pages, page offset 0x288
+# LE64-NORELAX: 20228: pcalau12i $a0, 16
+# LE64-NORELAX-NEXT: addi.d $a0, $a0, 648
+# LE64-NORELAX-NEXT: ld.d $ra, $a0, 0
+# LE64-NORELAX-NEXT: jirl $ra, $ra, 0
+# LE64-NORELAX-NEXT: add.d $a1, $a0, $tp
+
+## &.got[b]-. = 0x30288+48 - 0x2023c: 0x10 pages, page offset 0x2b8
+## R_LARCH_RELAX does not appear in pairs. No relaxation.
+# LE64-NORELAX: 2023c: pcalau12i $a0, 16
+# LE64-NORELAX-NEXT: addi.d $a0, $a0, 696
+# LE64-NORELAX-NEXT: ld.d $ra, $a0, 0
+# LE64-NORELAX-NEXT: jirl $ra, $ra, 0
+# LE64-NORELAX-NEXT: add.d $a2, $a0, $tp
+
+## &.got[c]-. = 0x30288+16 - 0x20250: 0x10 pages, page offset 0x298
+## Without R_LARCH_RELAX relocation. No relaxation.
+# LE64-NORELAX: 20250: pcalau12i $a0, 16
+# LE64-NORELAX-NEXT: addi.d $t0, $zero, 0
+# LE64-NORELAX-NEXT: addi.d $a0, $a0, 664
+# LE64-NORELAX-NEXT: addi.d $t0, $t0, 1
+# LE64-NORELAX-NEXT: ld.d $ra, $a0, 0
+# LE64-NORELAX-NEXT: addi.d $t0, $t0, 1
+# LE64-NORELAX-NEXT: jirl $ra, $ra, 0
+# LE64-NORELAX-NEXT: add.d $a3, $a0, $tp
+
+## &.got[d]-. = 0x30288+32 - 0x20270: 0x10 pages, page offset 0x2a8
+# LE64-NORELAX: 20270: pcalau12i $a0, 16
+# LE64-NORELAX-NEXT: addi.d $a0, $a0, 680
+# LE64-NORELAX-NEXT: ld.d $ra, $a0, 0
+# LE64-NORELAX-NEXT: jirl $ra, $ra, 0
+# LE64-NORELAX-NEXT: add.d $a4, $a0, $tp
+
+# IE64-RELA: .rela.dyn {
+# IE64-RELA-NEXT: 0x30430 R_LARCH_TLS_DESC64 - 0x8
+# IE64-RELA-NEXT: 0x30460 R_LARCH_TLS_DESC64 - 0x7FF
+# IE64-RELA-NEXT: 0x30440 R_LARCH_TLS_DESC64 c 0x0
+# IE64-RELA-NEXT: 0x30450 R_LARCH_TLS_DESC64 d 0x0
+# IE64-RELA-NEXT: }
+# IE64-RELA: Hex dump of section '.got':
+# IE64-RELA-NEXT: 0x00030430 00000000 00000000 00000000 00000000 .
+# IE64-RELA-NEXT: 0x00030440 00000000 00000000 00000000 00000000 .
+# IE64-RELA-NEXT: 0x00030450 00000000 00000000 00000000 00000000 .
+# IE64-RELA-NEXT: 0x00030460 00000000 00000000 00000000 00000000 .
+
+# IE64: .got 00000040 0000000000030430
+
+## a and b are optimized to use LE. c and d are optimized to IE.
+## &.got[a]-. = 0x30430 - 0x202f8 = 16462<<2
+# IE64: 202f8: pcaddi $a0, 16462
+# IE64-NEXT: ld.d $ra, $a0, 0
+# IE64-NEXT: jirl $ra, $ra, 0
+# IE64-NEXT: add.d $a1, $a0, $tp
+
+## &.got[b]-. = 0x30430+48 - 0x20308: 0x10 pages, page offset 0x460
+## R_LARCH_RELAX does not appear in pairs. No relaxation.
+# IE64: 20308: pcalau12i $a0, 16
+# IE64-NEXT: addi.d $a0, $a0, 1120
+# IE64-NEXT: ld.d $ra, $a0, 0
+# IE64-NEXT: jirl $ra, $ra, 0
+# IE64-NEXT: add.d $a2, $a0, $tp
+
+## &.got[c]-. = 0x30430+16 - 0x2031c: 0x10 pages, page offset 0x440
+## Without R_LARCH_RELAX relocation. No relaxation.
+# IE64: 2031c: pcalau12i $a0, 16
+# IE64-NEXT: addi.d $t0, $zero, 0
+# IE64-NEXT: addi.d $a0, $a0, 1088
+# IE64-NEXT: addi.d $t0, $t0, 1
+# IE64-NEXT: ld.d $ra, $a0, 0
+# IE64-NEXT: addi.d $t0, $t0, 1
+# IE64-NEXT: jirl $ra, $ra, 0
+# IE64-NEXT: add.d $a3, $a0, $tp
+
+## &.got[d]-. = 0x30430+32 - 0x2033c = 16453<<2
+# IE64: 2033c: pcaddi $a0, 16453
+# IE64-NEXT: ld.d $ra, $a0, 0
+# IE64-NEXT: jirl $ra, $ra, 0
+# IE64-NEXT: add.d $a4, $a0, $tp
+
+# IE64-NORELAX: .got 00000040 0000000000030438
+
+## &.got[a]-. = 0x30438 - 0x202f8 = 0x10 pages, page offset 0x438
+# IE64-NORELAX: 202f8: pcalau12i $a0, 16
+# IE64-NORELAX-NEXT: addi.d $a0, $a0, 1080
+# IE64-NORELAX-NEXT: ld.d $ra, $a0, 0
+# IE64-NORELAX-NEXT: jirl $ra, $ra, 0
+# IE64-NORELAX-NEXT: add.d $a1, $a0, $tp
+
+## &.got[b]-. = 0x30438+48 - 0x2030c: 0x10 pages, page offset 0x468
+## R_LARCH_RELAX does not appear in pairs. No relaxation.
+# IE64-NORELAX: 2030c: pcalau12i $a0, 16
+# IE64-NORELAX-NEXT: addi.d $a0, $a0, 1128
+# IE64-NORELAX-NEXT: ld.d $ra, $a0, 0
+# IE64-NORELAX-NEXT: jirl $ra, $ra, 0
+# IE64-NORELAX-NEXT: add.d $a2, $a0, $tp
+
+## &.got[c]-. = 0x30438+16 - 0x20320: 0x10 pages, page offset 0x448
+## Without R_LARCH_RELAX relocation. No relaxation.
+# IE64-NORELAX: 20320: pcalau12i $a0, 16
+# IE64-NORELAX-NEXT: addi.d $t0, $zero, 0
+# IE64-NORELAX-NEXT: addi.d $a0, $a0, 1096
+# IE64-NORELAX-NEXT: addi.d $t0, $t0, 1
+# IE64-NORELAX-NEXT: ld.d $ra, $a0, 0
+# IE64-NORELAX-NEXT: addi.d $t0, $t0, 1
+# IE64-NORELAX-NEXT: jirl $ra, $ra, 0
+# IE64-NORELAX-NEXT: add.d $a3, $a0, $tp
+
+## &.got[d]-. = 0x30438+32 - 0x20340: 0x10 pages, page offset 0x458
+# IE64-NORELAX: 20340: pcalau12i $a0, 16
+# IE64-NORELAX-NEXT: addi.d $a0, $a0, 1112
+# IE64-NORELAX-NEXT: ld.d $ra, $a0, 0
+# IE64-NORELAX-NEXT: jirl $ra, $ra, 0
+# IE64-NORELAX-NEXT: add.d $a4, $a0, $tp
+
+#--- a.s
+la.tls.desc $a0, a
+add.d $a1, $a0, $tp
+
+# ADDI.D does not have R_LARCH_RELAX. No relaxation.
+pcalau12i $a0, %desc_pc_hi20(b)
+.reloc .-4, R_LARCH_RELAX, 0
+addi.d $a0, $a0, %desc_pc_lo12(b)
+ld.d $ra, $a0, %desc_ld(b)
+jirl $ra, $ra, %desc_call(b)
+add.d $a2, $a0, $tp
+
+# TLSDESC to LE. No relaxation.
+pcalau12i $a0, %desc_pc_hi20(c)
+addi.d $t0, $zero, 0
+addi.d $a0, $a0, %desc_pc_lo12(c)
+addi.d $t0, $t0, 1
+ld.d $ra, $a0, %desc_ld(c)
+addi.d $t0, $t0, 1
+jirl $ra, $ra, %desc_call(c)
+add.d $a3, $a0, $tp
+
+# PCALAU12I and ADDI.D have R_LARCH_RELAX. We preform relaxation.
+pcalau12i $a0, %desc_pc_hi20(d)
+.reloc .-4, R_LARCH_RELAX, 0
+addi.d $a0, $a0, %desc_pc_lo12(d)
+.reloc .-4, R_LARCH_RELAX, 0
+ld.d $ra, $a0, %desc_ld(d)
+jirl $ra, $ra, %desc_call(d)
+add.d $a4, $a0, $tp
+
+.section .tbss,"awT", at nobits
+.globl a
+.zero 8
+a:
+.zero 2039 ## Place b at 0x7ff
+b:
+.zero 1
+
+#--- c.s
+.section .tbss,"awT", at nobits
+.globl c, d
+c:
+.zero 2048 ## Place d at 0x1000
+d:
+.zero 4
>From 0f580567169ffbf1546a5389ab4b9f7d1fc07c71 Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Thu, 2 Jan 2025 20:58:56 +0800
Subject: [PATCH 2/9] Convert TLS IE to LE in the normal or medium code model.
Original code sequence:
* pcalau12i $a0, %ie_pc_hi20(sym)
* ld.d $a0, $a0, %ie_pc_lo12(sym)
The code sequence converted is as follows:
* lu12i.w $a0, %ie_pc_hi20(sym) # le_hi20 != 0, otherwise NOP
* ori $a0 $a0, %ie_pc_lo12(sym)
FIXME: When relaxation enables, redundant NOP can be removed. This will
be implemented in a future patch.
Note: In the normal or medium code model, original code sequence with
relocations can appear interleaved, because converted code sequence
calculates the absolute offset. However, in extreme code model, to
identify the current code model, the first four instructions with
relocations must appear consecutively.
---
lld/ELF/Arch/LoongArch.cpp | 87 ++++++++++++++++++++++++++++++++++++++
lld/ELF/Relocations.cpp | 15 ++++++-
2 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp
index 4edc625b05cb0..f9a22a7bd5218 100644
--- a/lld/ELF/Arch/LoongArch.cpp
+++ b/lld/ELF/Arch/LoongArch.cpp
@@ -39,7 +39,11 @@ class LoongArch final : public TargetInfo {
void relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const override;
bool relaxOnce(int pass) const override;
+ void relocateAlloc(InputSectionBase &sec, uint8_t *buf) const override;
void finalizeRelax(int passes) const override;
+
+private:
+ void tlsIeToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
};
} // end anonymous namespace
@@ -53,6 +57,8 @@ enum Op {
ADDI_W = 0x02800000,
ADDI_D = 0x02c00000,
ANDI = 0x03400000,
+ ORI = 0x03800000,
+ LU12I_W = 0x14000000,
PCADDI = 0x18000000,
PCADDU12I = 0x1c000000,
LD_W = 0x28800000,
@@ -1002,6 +1008,87 @@ static bool relax(Ctx &ctx, InputSection &sec) {
return changed;
}
+// Convert TLS IE to LE in the normal or medium code model.
+// Original code sequence:
+// * pcalau12i $a0, %ie_pc_hi20(sym)
+// * ld.d $a0, $a0, %ie_pc_lo12(sym)
+//
+// The code sequence converted is as follows:
+// * lu12i.w $a0, %le_hi20(sym) # le_hi20 != 0, otherwise NOP
+// * ori $a0 $a0, %le_lo12(sym)
+//
+// When relaxation enables, redundant NOPs can be removed.
+void LoongArch::tlsIeToLe(uint8_t *loc, const Relocation &rel,
+ uint64_t val) const {
+ assert(isInt<32>(val) &&
+ "val exceeds the range of medium code model in tlsIeToLe");
+
+ bool isUInt12 = isUInt<12>(val);
+ const uint32_t currInsn = read32le(loc);
+ switch (rel.type) {
+ case R_LARCH_TLS_IE_PC_HI20:
+ if (isUInt12)
+ write32le(loc, insn(ANDI, R_ZERO, R_ZERO, 0)); // nop
+ else
+ write32le(loc, insn(LU12I_W, getD5(currInsn), extractBits(val, 31, 12),
+ 0)); // lu12i.w $a0, %le_hi20
+ break;
+ case R_LARCH_TLS_IE_PC_LO12:
+ if (isUInt12)
+ write32le(loc, insn(ORI, getD5(currInsn), R_ZERO,
+ val)); // ori $a0, $r0, %le_lo12
+ else
+ write32le(loc, insn(ORI, getD5(currInsn), getJ5(currInsn),
+ lo12(val))); // ori $a0, $a0, %le_lo12
+ break;
+ }
+}
+
+void LoongArch::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
+ const unsigned bits = ctx.arg.is64 ? 64 : 32;
+ uint64_t secAddr = sec.getOutputSection()->addr;
+ if (auto *s = dyn_cast<InputSection>(&sec))
+ secAddr += s->outSecOff;
+ else if (auto *ehIn = dyn_cast<EhInputSection>(&sec))
+ secAddr += ehIn->getParent()->outSecOff;
+ bool isExtreme = false;
+ const MutableArrayRef<Relocation> relocs = sec.relocs();
+ for (size_t i = 0, size = relocs.size(); i != size; ++i) {
+ Relocation &rel = relocs[i];
+ uint8_t *loc = buf + rel.offset;
+ uint64_t val = SignExtend64(
+ sec.getRelocTargetVA(ctx, rel, secAddr + rel.offset), bits);
+
+ switch (rel.expr) {
+ case R_RELAX_HINT:
+ continue;
+ case R_RELAX_TLS_IE_TO_LE:
+ if (rel.type == R_LARCH_TLS_IE_PC_HI20) {
+ // LoongArch does not support IE to LE optimize in the extreme code
+ // model. In this case, the relocs are as follows:
+ //
+ // * i -- R_LARCH_TLS_IE_PC_HI20
+ // * i+1 -- R_LARCH_TLS_IE_PC_LO12
+ // * i+2 -- R_LARCH_TLS_IE64_PC_LO20
+ // * i+3 -- R_LARCH_TLS_IE64_PC_HI12
+ isExtreme =
+ (i + 2 < size && relocs[i + 2].type == R_LARCH_TLS_IE64_PC_LO20);
+ }
+ if (isExtreme) {
+ rel.expr = getRelExpr(rel.type, *rel.sym, loc);
+ val = SignExtend64(sec.getRelocTargetVA(ctx, rel, secAddr + rel.offset),
+ bits);
+ relocateNoSym(loc, rel.type, val);
+ } else
+ tlsIeToLe(loc, rel, val);
+ continue;
+ default:
+ break;
+ }
+ relocate(loc, rel, val);
+ }
+}
+
// When relaxing just R_LARCH_ALIGN, relocDeltas is usually changed only once in
// the absence of a linker script. For call and load/store R_LARCH_RELAX, code
// shrinkage may reduce displacement and make more relocations eligible for
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 629702b45965b..19d2c6d2f0fda 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1375,6 +1375,11 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr expr, RelType type,
return 1;
}
+ // LoongArch support IE to LE optimization in non-extreme code model.
+ bool execOptimizeInLoongArch =
+ ctx.arg.emachine == EM_LOONGARCH &&
+ (type == R_LARCH_TLS_IE_PC_HI20 || type == R_LARCH_TLS_IE_PC_LO12);
+
// ARM, Hexagon, LoongArch and RISC-V do not support GD/LD to IE/LE
// optimizations.
// RISC-V supports TLSDESC to IE/LE optimizations.
@@ -1382,7 +1387,7 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr expr, RelType type,
// optimization as well.
bool execOptimize =
!ctx.arg.shared && ctx.arg.emachine != EM_ARM &&
- ctx.arg.emachine != EM_HEXAGON && ctx.arg.emachine != EM_LOONGARCH &&
+ ctx.arg.emachine != EM_HEXAGON && execOptimizeInLoongArch &&
!(isRISCV && expr != R_TLSDESC_PC && expr != R_TLSDESC_CALL) &&
!sec->file->ppc64DisableTLSRelax;
@@ -1457,6 +1462,14 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr expr, RelType type,
return ctx.target->getTlsGdRelaxSkip(type);
}
+ // LoongArch TLS GD/LD relocs reuse the RE_LOONGARCH_TLSGD_PAGE_PC, in which
+ // NEEDS_TLSIE shouldn't set. So we check independently.
+ if (ctx.arg.emachine == EM_LOONGARCH && expr == RE_LOONGARCH_GOT &&
+ execOptimize && isLocalInExecutable) {
+ sec->addReloc({R_RELAX_TLS_IE_TO_LE, type, offset, addend, &sym});
+ return 1;
+ }
+
if (oneof<R_GOT, R_GOTPLT, R_GOT_PC, RE_AARCH64_GOT_PAGE_PC,
RE_LOONGARCH_GOT_PAGE_PC, R_GOT_OFF, R_TLSIE_HINT>(expr)) {
ctx.hasTlsIe.store(true, std::memory_order_relaxed);
>From 441f1bc7fc4d0b9ff80d4456a64c3f56dd0479fc Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Fri, 3 Jan 2025 09:11:11 +0800
Subject: [PATCH 3/9] Test loongarch-tls-ie.s pass.
---
lld/test/ELF/loongarch-tls-ie.s | 30 ++++++++++++------------------
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a/lld/test/ELF/loongarch-tls-ie.s b/lld/test/ELF/loongarch-tls-ie.s
index 78c207991b4e6..ddfd9c976cb9b 100644
--- a/lld/test/ELF/loongarch-tls-ie.s
+++ b/lld/test/ELF/loongarch-tls-ie.s
@@ -12,7 +12,7 @@
## LA32 IE -> LE
# RUN: ld.lld %t/32.o -o %t/32
# RUN: llvm-readelf -r %t/32 | FileCheck --check-prefix=NOREL %s
-# RUN: llvm-readelf -x .got %t/32 | FileCheck --check-prefix=LE32-GOT %s
+# RUN: llvm-readelf -x .got %t/32 2>&1 | FileCheck --check-prefix=LE32-GOT %s
# RUN: llvm-objdump -d --no-show-raw-insn %t/32 | FileCheck --check-prefixes=LE32 %s
## LA64 IE
@@ -23,7 +23,7 @@
## LA64 IE -> LE
# RUN: ld.lld %t/64.o -o %t/64
# RUN: llvm-readelf -r %t/64 | FileCheck --check-prefix=NOREL %s
-# RUN: llvm-readelf -x .got %t/64 | FileCheck --check-prefix=LE64-GOT %s
+# RUN: llvm-readelf -x .got %t/64 2>&1 | FileCheck --check-prefix=LE64-GOT %s
# RUN: llvm-objdump -d --no-show-raw-insn %t/64 | FileCheck --check-prefixes=LE64 %s
# IE32-REL: FLAGS STATIC_TLS
@@ -62,29 +62,23 @@
# a at tprel = st_value(a) = 0x8
# b at tprel = st_value(a) = 0xc
-# LE32-GOT: section '.got':
-# LE32-GOT-NEXT: 0x0003012c 08000000 0c000000
-# LE64-GOT: section '.got':
-# LE64-GOT-NEXT: 0x000301e0 08000000 00000000 0c000000 00000000
+# LE32-GOT: could not find section '.got'
+# LE64-GOT: could not find section '.got'
## LA32:
-## &.got[0] - . = 0x3012c - 0x20114: 0x10 pages, page offset 0x12c
-## &.got[1] - . = 0x30130 - 0x20120: 0x10 pages, page offset 0x130
-# LE32: 20114: pcalau12i $a4, 16
-# LE32-NEXT: ld.w $a4, $a4, 300
+# LE32: 200d4: nop
+# LE32-NEXT: ori $a4, $zero, 8
# LE32-NEXT: add.w $a4, $a4, $tp
-# LE32-NEXT: 20120: pcalau12i $a5, 16
-# LE32-NEXT: ld.w $a5, $a5, 304
+# LE32-NEXT: 200e0: nop
+# LE32-NEXT: ori $a5, $zero, 12
# LE32-NEXT: add.w $a5, $a5, $tp
## LA64:
-## &.got[0] - . = 0x301e0 - 0x201c8: 0x10 pages, page offset 0x1e0
-## &.got[1] - . = 0x301e8 - 0x201d4: 0x10 pages, page offset 0x1e8
-# LE64: 201c8: pcalau12i $a4, 16
-# LE64-NEXT: ld.d $a4, $a4, 480
+# LE64: 20158: nop
+# LE64-NEXT: ori $a4, $zero, 8
# LE64-NEXT: add.d $a4, $a4, $tp
-# LE64-NEXT: 201d4: pcalau12i $a5, 16
-# LE64-NEXT: ld.d $a5, $a5, 488
+# LE64-NEXT: 20164: nop
+# LE64-NEXT: ori $a5, $zero, 12
# LE64-NEXT: add.d $a5, $a5, $tp
#--- 32.s
>From d17de7816159c1b7cb20bb994f3c92c351bda849 Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Fri, 3 Jan 2025 10:03:44 +0800
Subject: [PATCH 4/9] Add test loongarch-relax-tls-ie.s
---
lld/test/ELF/loongarch-relax-tls-ie.s | 70 +++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 lld/test/ELF/loongarch-relax-tls-ie.s
diff --git a/lld/test/ELF/loongarch-relax-tls-ie.s b/lld/test/ELF/loongarch-relax-tls-ie.s
new file mode 100644
index 0000000000000..f5375ae3a3b40
--- /dev/null
+++ b/lld/test/ELF/loongarch-relax-tls-ie.s
@@ -0,0 +1,70 @@
+# REQUIRES: loongarch
+## Test LA64 IE -> LE in various cases.
+
+# RUN: llvm-mc --filetype=obj --triple=loongarch64 -mattr=+relax %s -o %t.o
+
+## FIXME: IE relaxation has not yet been implemented.
+## --relax/--no-relax has the same result. Also check --emit-relocs.
+# RUN: ld.lld --emit-relocs %t.o -o %t
+# RUN: llvm-readelf -x .got %t 2>&1 | FileCheck --check-prefix=LE-GOT %s
+# RUN: llvm-objdump -dr --no-show-raw-insn %t | FileCheck --check-prefixes=LE %s
+
+# RUN: ld.lld --emit-relocs --no-relax %t.o -o %t.norelax
+# RUN: llvm-readelf -x .got %t.norelax 2>&1 | FileCheck --check-prefix=LE-GOT %s
+# RUN: llvm-objdump -dr --no-show-raw-insn %t.norelax | FileCheck --check-prefixes=LE %s
+
+# LE-GOT: could not find section '.got'
+
+# a at tprel = st_value(a) = 0xfff
+# b at tprel = st_value(a) = 0x1000
+# LE: 20158: nop
+# LE-NEXT: R_LARCH_TLS_IE_PC_HI20 a
+# LE-NEXT: R_LARCH_RELAX *ABS*
+# LE-NEXT: ori $a0, $zero, 4095
+# LE-NEXT: R_LARCH_TLS_IE_PC_LO12 a
+# LE-NEXT: R_LARCH_RELAX *ABS*
+# LE-NEXT: add.d $a0, $a0, $tp
+# LE-NEXT: 20164: lu12i.w $a1, 1
+# LE-NEXT: R_LARCH_TLS_IE_PC_HI20 b
+# LE-NEXT: ori $a1, $a1, 0
+# LE-NEXT: R_LARCH_TLS_IE_PC_LO12 b
+# LE-NEXT: add.d $a1, $a1, $tp
+# LE-NEXT: 20170: nop
+# LE-NEXT: R_LARCH_TLS_IE_PC_HI20 a
+# LE-NEXT: R_LARCH_RELAX *ABS*
+# LE-NEXT: lu12i.w $a3, 1
+# LE-NEXT: R_LARCH_TLS_IE_PC_HI20 b
+# LE-NEXT: R_LARCH_RELAX *ABS*
+# LE-NEXT: ori $a2, $zero, 4095
+# LE-NEXT: R_LARCH_TLS_IE_PC_LO12 a
+# LE-NEXT: ori $a3, $a3, 0
+# LE-NEXT: R_LARCH_TLS_IE_PC_LO12 b
+# LE-NEXT: add.d $a2, $a2, $tp
+# LE-NEXT: add.d $a3, $a3, $tp
+
+la.tls.ie $a0, a # relax
+add.d $a0, $a0, $tp
+
+# PCALAU12I does not have R_LARCH_RELAX. No relaxation.
+pcalau12i $a1, %ie_pc_hi20(b)
+ld.d $a1, $a1, %ie_pc_lo12(b)
+add.d $a1, $a1, $tp
+
+# Test instructions are interleaved.
+# PCALAU12I has an R_LARCH_RELAX. We preform relaxation.
+pcalau12i $a2, %ie_pc_hi20(a)
+.reloc .-4, R_LARCH_RELAX, 0
+pcalau12i $a3, %ie_pc_hi20(b)
+.reloc .-4, R_LARCH_RELAX, 0
+ld.d $a2, $a2, %ie_pc_lo12(a)
+ld.d $a3, $a3, %ie_pc_lo12(b)
+add.d $a2, $a2, $tp
+add.d $a3, $a3, $tp
+
+.section .tbss,"awT", at nobits
+.globl a
+.zero 0xfff ## Place a at 0xfff, LE needs only one ins.
+a:
+.zero 1 ## Place b at 0x1000, LE needs two ins.
+b:
+.zero 4
>From 20b544c6df789763518299ceb0183b870c223f0a Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Fri, 3 Jan 2025 16:25:15 +0800
Subject: [PATCH 5/9] modify RE_LOONGARCH_GOT.
---
lld/ELF/Relocations.cpp | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 19d2c6d2f0fda..be0931c2123f0 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1462,14 +1462,6 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr expr, RelType type,
return ctx.target->getTlsGdRelaxSkip(type);
}
- // LoongArch TLS GD/LD relocs reuse the RE_LOONGARCH_TLSGD_PAGE_PC, in which
- // NEEDS_TLSIE shouldn't set. So we check independently.
- if (ctx.arg.emachine == EM_LOONGARCH && expr == RE_LOONGARCH_GOT &&
- execOptimize && isLocalInExecutable) {
- sec->addReloc({R_RELAX_TLS_IE_TO_LE, type, offset, addend, &sym});
- return 1;
- }
-
if (oneof<R_GOT, R_GOTPLT, R_GOT_PC, RE_AARCH64_GOT_PAGE_PC,
RE_LOONGARCH_GOT_PAGE_PC, R_GOT_OFF, R_TLSIE_HINT>(expr)) {
ctx.hasTlsIe.store(true, std::memory_order_relaxed);
@@ -1489,6 +1481,15 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr expr, RelType type,
return 1;
}
+ // LoongArch TLS GD/LD relocs reuse the RE_LOONGARCH_GOT, in which
+ // NEEDS_TLSIE shouldn't set. So we check independently.
+ if (ctx.arg.emachine == EM_LOONGARCH && expr == RE_LOONGARCH_GOT &&
+ execOptimize && isLocalInExecutable) {
+ ctx.hasTlsIe.store(true, std::memory_order_relaxed);
+ sec->addReloc({R_RELAX_TLS_IE_TO_LE, type, offset, addend, &sym});
+ return 1;
+ }
+
return 0;
}
>From 5dafc6640c355827ca9de75b2a29b617c909431d Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Tue, 21 Jan 2025 13:52:55 +0800
Subject: [PATCH 6/9] Fix bug.
---
lld/ELF/Relocations.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index be0931c2123f0..259b8f4e758df 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1387,7 +1387,8 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr expr, RelType type,
// optimization as well.
bool execOptimize =
!ctx.arg.shared && ctx.arg.emachine != EM_ARM &&
- ctx.arg.emachine != EM_HEXAGON && execOptimizeInLoongArch &&
+ ctx.arg.emachine != EM_HEXAGON &&
+ (ctx.arg.emachine != EM_LOONGARCH || execOptimizeInLoongArch) &&
!(isRISCV && expr != R_TLSDESC_PC && expr != R_TLSDESC_CALL) &&
!sec->file->ppc64DisableTLSRelax;
>From 46f34a90ae7ca02fd57b59a0c38c570d0627f27f Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Thu, 20 Mar 2025 17:52:49 +0800
Subject: [PATCH 7/9] Fixes for review
---
lld/ELF/Arch/LoongArch.cpp | 11 ++++++-----
lld/ELF/Relocations.cpp | 2 +-
lld/test/ELF/loongarch-relax-tls-ie.s | 2 +-
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp
index f9a22a7bd5218..e60b4b4d028ff 100644
--- a/lld/ELF/Arch/LoongArch.cpp
+++ b/lld/ELF/Arch/LoongArch.cpp
@@ -1014,8 +1014,8 @@ static bool relax(Ctx &ctx, InputSection &sec) {
// * ld.d $a0, $a0, %ie_pc_lo12(sym)
//
// The code sequence converted is as follows:
-// * lu12i.w $a0, %le_hi20(sym) # le_hi20 != 0, otherwise NOP
-// * ori $a0 $a0, %le_lo12(sym)
+// * lu12i.w $a0, %le_hi20(sym) # le_hi20 != 0, otherwise NOP
+// * ori $a0, src, %le_lo12(sym) # le_hi20 != 0, src = $a0, otherwise src = $zero
//
// When relaxation enables, redundant NOPs can be removed.
void LoongArch::tlsIeToLe(uint8_t *loc, const Relocation &rel,
@@ -1036,7 +1036,7 @@ void LoongArch::tlsIeToLe(uint8_t *loc, const Relocation &rel,
case R_LARCH_TLS_IE_PC_LO12:
if (isUInt12)
write32le(loc, insn(ORI, getD5(currInsn), R_ZERO,
- val)); // ori $a0, $r0, %le_lo12
+ val)); // ori $a0, $zero, %le_lo12
else
write32le(loc, insn(ORI, getD5(currInsn), getJ5(currInsn),
lo12(val))); // ori $a0, $a0, %le_lo12
@@ -1064,7 +1064,7 @@ void LoongArch::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
continue;
case R_RELAX_TLS_IE_TO_LE:
if (rel.type == R_LARCH_TLS_IE_PC_HI20) {
- // LoongArch does not support IE to LE optimize in the extreme code
+ // LoongArch does not support IE to LE optimization in the extreme code
// model. In this case, the relocs are as follows:
//
// * i -- R_LARCH_TLS_IE_PC_HI20
@@ -1079,8 +1079,9 @@ void LoongArch::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
val = SignExtend64(sec.getRelocTargetVA(ctx, rel, secAddr + rel.offset),
bits);
relocateNoSym(loc, rel.type, val);
- } else
+ } else {
tlsIeToLe(loc, rel, val);
+ }
continue;
default:
break;
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 259b8f4e758df..41f8f656b0100 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1375,7 +1375,7 @@ unsigned RelocationScanner::handleTlsRelocation(RelExpr expr, RelType type,
return 1;
}
- // LoongArch support IE to LE optimization in non-extreme code model.
+ // LoongArch supports IE to LE optimization in non-extreme code model.
bool execOptimizeInLoongArch =
ctx.arg.emachine == EM_LOONGARCH &&
(type == R_LARCH_TLS_IE_PC_HI20 || type == R_LARCH_TLS_IE_PC_LO12);
diff --git a/lld/test/ELF/loongarch-relax-tls-ie.s b/lld/test/ELF/loongarch-relax-tls-ie.s
index f5375ae3a3b40..82e609d005aff 100644
--- a/lld/test/ELF/loongarch-relax-tls-ie.s
+++ b/lld/test/ELF/loongarch-relax-tls-ie.s
@@ -51,7 +51,7 @@ ld.d $a1, $a1, %ie_pc_lo12(b)
add.d $a1, $a1, $tp
# Test instructions are interleaved.
-# PCALAU12I has an R_LARCH_RELAX. We preform relaxation.
+# PCALAU12I has an R_LARCH_RELAX. We perform relaxation.
pcalau12i $a2, %ie_pc_hi20(a)
.reloc .-4, R_LARCH_RELAX, 0
pcalau12i $a3, %ie_pc_hi20(b)
>From 6b567c2a09198d16b599c89d6d1c333dfd17b2a6 Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Thu, 20 Mar 2025 18:02:51 +0800
Subject: [PATCH 8/9] code format
---
lld/ELF/Arch/LoongArch.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp
index e60b4b4d028ff..6fdcbaa984501 100644
--- a/lld/ELF/Arch/LoongArch.cpp
+++ b/lld/ELF/Arch/LoongArch.cpp
@@ -1015,7 +1015,8 @@ static bool relax(Ctx &ctx, InputSection &sec) {
//
// The code sequence converted is as follows:
// * lu12i.w $a0, %le_hi20(sym) # le_hi20 != 0, otherwise NOP
-// * ori $a0, src, %le_lo12(sym) # le_hi20 != 0, src = $a0, otherwise src = $zero
+// * ori $a0, src, %le_lo12(sym) # le_hi20 != 0, src = $a0,
+// # otherwise, src = $zero
//
// When relaxation enables, redundant NOPs can be removed.
void LoongArch::tlsIeToLe(uint8_t *loc, const Relocation &rel,
>From 351a9c23316dcc5b9dd9414ce305acd5a82012da Mon Sep 17 00:00:00 2001
From: yangzhaoxin <yangzhaoxin at loongson.cn>
Date: Fri, 21 Mar 2025 08:49:39 +0800
Subject: [PATCH 9/9] modify `tlsIeToLe` type to static
---
lld/ELF/Arch/LoongArch.cpp | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp
index 6fdcbaa984501..86f1778112a32 100644
--- a/lld/ELF/Arch/LoongArch.cpp
+++ b/lld/ELF/Arch/LoongArch.cpp
@@ -41,9 +41,6 @@ class LoongArch final : public TargetInfo {
bool relaxOnce(int pass) const override;
void relocateAlloc(InputSectionBase &sec, uint8_t *buf) const override;
void finalizeRelax(int passes) const override;
-
-private:
- void tlsIeToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const;
};
} // end anonymous namespace
@@ -1019,8 +1016,7 @@ static bool relax(Ctx &ctx, InputSection &sec) {
// # otherwise, src = $zero
//
// When relaxation enables, redundant NOPs can be removed.
-void LoongArch::tlsIeToLe(uint8_t *loc, const Relocation &rel,
- uint64_t val) const {
+static void tlsIeToLe(uint8_t *loc, const Relocation &rel, uint64_t val) {
assert(isInt<32>(val) &&
"val exceeds the range of medium code model in tlsIeToLe");
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